JPS63179679A - Digital vtr - Google Patents

Abstract

PURPOSE:To obtain a reproduced picture with high quality at high speed reproduction by recording a recording data whose compression rate is decreased nearly to one-half of the compression rate of the recording data recorded on other track onto a track located at tape edge. CONSTITUTION:A quantization circuit 9A applying coding to a digital video signal for high efficient coding by a 1st compression rate and a quantizing circuit 9B applying coding to the digital video signal for highly efficient coding with the 2nd compression rate nearly one-half of the 1st compression rate are provided. Then the recording data processed by the 2nd compression rate is recorded onto a track located one and other tape edges and a recording data processed by the 1st compression rate is recorded on the other track not located at the tape edge. Thus, in case of the track located at the tape edge, the digital video signal by one frame is recorded as two tracks. Thus, the tracks located on the tape edge are reproduced consecutively at high speed reproduction and a restored picture is obtained from a data with a low compression rate, the reproduced picture with high quality is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital VTR, and particularly to a digital VTR that compresses the amount of information by encoding a digital video signal with a high-efficiency code.

[Summary of the invention]

In this invention, a plurality of tracks of a predetermined length are sequentially formed from one tape edge toward the other tape edge, and then a plurality of tracks of a predetermined length are sequentially formed from the other tape edge toward one tape edge. In a digital VTR that records repeatedly,
The tracks located on one tape edge and the other tape edge record data that has been processed at a compression rate approximately equal to that of the digital video signal recorded on the other track, resulting in high-speed playback with good image quality. It is done.

[Conventional technology]

As one type of rotary head type VTR, a configuration has been proposed in which a rotary head moves up and down and tracks of a predetermined length are sequentially formed in the width direction of a magnetic tape.

In this type of VTR, high-speed playback operations are performed by continuously scanning tracks located at the upper or lower edge of the tape. Since there is a large amount of information in a digital video signal, it is conceivable to compress the amount of information in the digital video signal when recording/reproducing the digital video signal using the above rotary head type VTR. For example, a high-efficiency encoding device that performs variable length encoding adapted to the dynamic range of a block as described in Japanese Patent Application No. 60-268817 can be used.

A high-efficiency encoding device that performs encoding adapted to the dynamic range of this block calculates the dynamic range defined by the maximum and minimum values of multiple pixels included in the block, and divides the dynamic range into multiple level ranges. Then, a code signal corresponding to the level range to which the pixel data after minimum value removal belongs is formed. In this case, the number of bits of the code signal is changed according to the dynamic range so that the maximum distortion that occurs when quantization is approximately constant.

A high-efficiency code (A
DRC) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. In particular, variable length ADRC can increase the compression rate.

[Problem that the invention seeks to solve]

However, even if variable length ADRC is used, the original digital video signal for one frame, for example, can be
Since the images are compressed and recorded on the track, deterioration in the quality of the reproduced images cannot be avoided.

In particular, during high-speed playback, only the tracks located at the edges of the tape are scanned to obtain a reproduced image, which has the disadvantage of significant deterioration in image quality.

Therefore, an object of the present invention is to focus on the fact that the track to be scanned is a track located on one of the tape edges in the case of a high-speed playback operation. The object of the present invention is to provide a digital VTR that can obtain high-quality reproduced images during high-speed reproduction by recording record data with a compression rate reduced to approximately % of the data compression rate.

[Means for solving problems]

In this invention, a plurality of tracks of a predetermined length are sequentially formed from one tape edge toward the other tape edge, and then a plurality of tracks of a predetermined length are sequentially formed from the other tape edge toward one tape edge. In a digital VTR that records repeatedly,
a quantization circuit that encodes a digital video signal with a high-efficiency code at a first compression rate; and a quantization circuit for performing quantization, and recorded data processed at a second compression rate is recorded in tracks located at one tape edge and the other tape edge,
Recorded data processed at the first compression rate is recorded in other tracks that are not located at the tape edge.

[Effect]

For example, one frame worth of digital video signals is stored on each track formed other than the tape edge using a variable length AD.
The data is compressed by RC, and this compressed recording data is recorded. Also, for tracks located at the edge of the tape, the compression ratio is lowered to approximately 2 of the compression ratio of other tracks. A video signal is recorded. During high-speed playback, the tracks located at the tape edges are played back continuously, and a restored image is obtained from data with a low compression ratio, so that a high-quality reproduced image can be obtained.

〔Example〕

A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This explanation is made according to the following items.

a. ADRC encoder and ADRC decoder b. Variable length quantization and buffering C. Drum mechanism and recording pattern d. Modification a. ADRC encoder and ADRC decoder In FIG. A bit quantized digital video signal is supplied, and the input digital video signal is supplied to a blocking circuit 2. The blocking circuit 2 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding. In the blocking circuit 2, for example, (57
One frame of screen (0 lines x 720 pixels) is subdivided into (M x N) blocks as shown in FIG.

For example, as shown in FIG. 3, the l block has a size of (4 lines x 4 pixels). From blocking circuit 2, Bll+ +31L B+ff...BN
A converted digital video signal is generated in an order of M blocks.

A maximum value detection circuit 3 for detecting the maximum value MAX of the output signal of the blocking circuit 2 for each block. The signal is supplied to a minimum value detection circuit 4 and a delay circuit 5, which detect the minimum value MIN for each block. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 6, and a dynamic range DR expressed as (MAX-MIN-DR) is obtained from the subtraction circuit 6. The delay circuit 5 delays the data for the time necessary to detect the maximum value MAX and the minimum value MIN. The minimum value MIN is subtracted from the video data from the delay circuit 5 in a subtraction circuit 7, and the data PDI after the minimum value is removed is obtained from the subtraction circuit 7.

Data PDI after minimum value removal is supplied to quantization circuits 9A and 9B via delay circuit 8. The quantization circuits 9A and 9B are supplied with data of quantization widths Δa and Δb from ROMIIA and IIB, respectively. The quantization circuits 9A and 9B perform variable length ADRC encoding to quantize the data PDI using quantization widths Δa and Δb, respectively, that is,
The quantization circuits 9A and 9B generate pixel data PDI from which the minimum value MIN shared by the pixel data in the block is removed.
is divided by the quantization widths Δa and Δb, and a variable number of bits is quantized according to the dynamic range DR of the block.

Since the quantization width Δb is set to A with respect to the quantization width Δa, the compression rate of ADRC encoding performed by the quantization circuit 9B is equal to A of the compression rate of ADRC encoding performed by the quantization circuit 9A. Become. In other words, if the number of bits of the code signal DTa output from the quantization circuit 9A is (0 to 4 bits), then the number of bits of the code signal DTb output from the quantization circuit 9B is (0 to 8 bits). There is.

Since the video signal within a block has two-dimensional correlation and three-dimensional correlation, the dynamic range DR becomes smaller compared to the original data value, and is quantized using fewer than 8 bits. Also, quantization distortion is not noticeable. The quantization circuits 9A and 9B are composed of, for example, ROM. From the quantization circuits 9A and 9B, the maximum number of bits is 4.
Bit and 8-bit code signals DTa and DTb are generated, respectively. Code signals DTa and DTb from quantization circuits 9A and 9B are supplied to input terminals a and b of a switch circuit 14B, respectively. The code signal selected by the switch circuit 14B is supplied to the framing circuit 16.

Valid bits from the output signals of the quantization circuits 9A and 9B are selected in the subsequent framing circuit 16. Therefore, in ROMIIA and IIB, the quantization widths Δa and Δ
Data Na and Nb indicating the number of bits of the block are formed together with b.

These data Na and Nb are supplied to input terminals a and b of the switch circuit 14, respectively, and data selected by the switch circuit 14A is supplied to the framing circuit 16.

Switch circuits 14a and 14b are controlled by a control signal from terminal 15.

This control signal has different levels when the rotary head of the VTR scans a track located at the tape edge of the magnetic tape and when it scans other tracks. When the switch circuits 14A and 14B record digital data from the output terminal 17 on a track located at the tape edge, the input terminal and the output terminal C are connected, and the switch circuits 14A and 14B record digital data on a track other than the track located at the tape edge. At this time, input terminal a and output terminal C are connected.

With digital VTRs, the transmission rate of recorded data is constant, so if the amount of transmitted data is not limited, some data may not be recorded, or the quality of the reproduced image will deteriorate due to unnecessarily high compression rates. I do things. Therefore, the buffering circuit 10 is provided, and the buffering circuit 10
In this step, the frequency distribution of the dynamic range DR of all blocks of one screen to be ADRC encoded is examined, and optimal variable length encoding is performed.

The dynamic range DR is supplied to the buffering circuit 10 from the subtraction circuit 6. Buffering circuit 10
Then, the threshold values Tl, T2 . T3. T4 is determined, and a parameter code Pi corresponding to this threshold value is output. The parameter code Pl and the dynamic range DR of the block are supplied to the ROMs 11A and IIB, and the quantization widths Δa and Δb are read from the ROMIIA and IIB, respectively.

The compression rate of the ADRC encoding performed by the quantization circuit 9B is % compared to the ADRC encoding performed by the child conversion circuit 9A, but as will be described later, the code signal DTb from the quantization circuit 9B is Since data is recorded on two tracks located at the tape edge, common processing is performed regarding buffering.

The delay circuits 12 and 13 delay the dynamic range DR and the minimum value MIN until the optimum threshold value is determined by the buffering circuit 10 and variable length quantization is performed. Parameter code Pi from buffering circuit 10 and dynamic range D from delay circuit 12゜13
R and the minimum 41 CMIN, the data of the number of bits from the switch circuit 14A, and the code signal from the switch circuit 14B are supplied to the framing circuit 16.

The framing circuit 16 includes a code signal as variable length data and additional codes Pi, DR, M as fixed length data.
Encoding the IN for error correction and adding a synchronization signal. Transmission data is available at the output terminal 17 of the framing circuit 16. One parameter code Pi on one screen
is transmitted, DR and MIN data are transmitted for each block, and a code signal DT is transmitted for each pixel. Further, in the framing circuit 1G, as described above, valid bits of the code signal from the switch circuit 14B are selected using data indicating the number of bits from the switch circuit 14A.

The received data is supplied to an input terminal indicated by 21 in FIG.
T (DTa or DTb) and the minimum value MIN. The decoding circuit 23 receives the code signals DTa and DTb inversely to the quantization circuits 9A and 9B of the ADRC encoder.
Convert each of them to a restoration level. The restoration level from the decoding circuit 23 is supplied to the addition circuit 25, the minimum value MIN is added to the restoration level, and the restoration data from the addition circuit 25 is supplied to the block decomposition circuit 26.

Output data in the same order as the television signal is obtained from the output terminal 27 of the block decomposition circuit 26.

b. Variable length quantization and buffering FIG. 5 explains variable length quantization performed in the quantization circuit 9A. T2. T3 and T4 are thresholds for determining the number of allocated bits, respectively. These threshold values have the relationship (T, i<T3<T2<Tl).

When the dynamic range DR is (DR=74-1), as shown in Figure 5A, the maximum value MAX and the minimum value MIN
On the receiving side, the intermediate level LO between the two is transmitted.
is considered the restoration level. Therefore, as shown in FIG. 5A, when the dynamic range DR is (T4-1), the quantization width is Δ0. Dynamic range DR is (0≦
If DR≦T4-1), the number of allocated bits is O bits.

FIG. 5B shows a case where the dynamic range DR is (T3-1), and the dynamic range DR is (T4≦DR≦
73-1), the number of allocated bits is 1 bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the level range to which the pixel data PD■ after removing the minimum value of the block belongs to the quantization width (Δa=
Δl) and the level range and corresponding “0”
or "l" is assigned, and the restoration level is set to LO or Ll.

In the variable length coding shown in FIG. 5, the larger the dynamic range, the smaller the quantization width Δa (Δ0
Non-linear quantization is performed, which is increased as Δ3 Δ4). Non-linear quantization reduces the maximum distortion for blocks with a small dynamic range where quantization distortion is easily noticeable, and conversely increases the maximum distortion for blocks with a large dynamic range, resulting in a higher compression ratio. be destroyed.

When the dynamic range DR is (T 2-1 ), the detected dynamic range DR is divided into four level ranges, as shown in FIG. (00)(01)(l 0)(1
1) is assigned, and the center level of each level range is set as the restoration level LO, Ll, L2°L3. Therefore, the level range to which the data PDI belongs is checked using the quantization width (Δa-Δ2). The dynamic range DR is (T
In the case of 3≦DR≦72-1), the number of allocated bits is 2 bits.

Furthermore, when the dynamic range DR is (TI-1), the detected dynamic range DR is divided into eight level ranges, and 3 bits ( 000)(001)...
- (111) is assigned, and the center level of each level range is set as the restoration level LO, Ll...Ll. Therefore, the quantization width Δa becomes Δ3. Dynamic range D
When R is (T2≦DR≦Tl-1), the number of allocated bits is 3 bits.

Furthermore, when the dynamic range is maximum 255,
As shown in FIG. 5E, the detected dynamic range DR is divided into 16 level ranges, and for each level range, 4 pips
... (1111) are assigned, and the center level of each level range is set as the restoration level LO, L1...Ll5. Therefore, the quantization width Δa becomes Δ4. When the dynamic range DR is (TI≦DR≦255), the number of allocated bits is 4 bits.

As thresholds Tl to T4, for example, when the highest transmission rate is (2 bits/pixel), the parameter code P
The following 11 sets, distinguished by i, are prepared.

Among the thresholds mentioned above, the parameter code P.

The set of threshold values specified by can minimize quantization distortion the most. In the buffering circuit lO, the frequency distribution of the dynamic range DR of all blocks within l frame is determined. Parameter code P for this frequency distribution
Code signal DTa (or DTb) when ADRC encoding is performed by sequentially applying the threshold values shown in 1
The total number of bits (occurrence information) is calculated. This amount of generated information is compared with a data threshold known in advance, and a set of thresholds with as small distortion as possible without exceeding the data threshold is determined. be done.

That is, among the number of blocks included in the five ranges of the dynamic range DR divided by the threshold value Tl - T4, each number of blocks excluding the number of blocks to which 0 bits are allocated is multiplied by the number of allocated bits. The amount of generated information can be determined by This amount of generated information is compared with a data threshold, and when the data threshold is exceeded, a larger set of thresholds is applied and the amount of generated information is calculated in the same way.

C. Drum mechanism and recording pattern FIG. 6 schematically shows the drum mechanism of the rotary head type VTR in this embodiment.
indicates a tape guide drum. A magnetic tape (not shown) is wound around the circumferential surface of a tape guide drum 31, and rotary heads 32a and 32b scan the magnetic tape. rotating head 3
2a and 32b are rotated by a motor 33. Also,
The tape guide drum 31 and the motor 33 are integrated into the motor 3.
It is moved up and down by 4. 35 is a gear for vertically moving the tape guide drum 31 and the motor 33 by the motor 34.

The recording pattern of a VTR having the above-mentioned drum mechanism is shown in FIG. In FIG. 7, the track width W in the width direction of the magnetic tape is indicated by 36.

Tracks of track length are sequentially formed as shown by the arrows. For example, one frame of data is recorded on one tree track. However, in the case of tracks located at the tape edges marked with diagonal lines, one frame's worth of data is recorded on two tracks.

During recording and normal reproduction, the rotary heads 32a and 32b scan the magnetic tape 36 in the order indicated by the arrows.

Further, during high-speed reproduction, the tape guide drum 31 and the motor 33 do not move up and down, and only the track located at one of the upper and lower tape edges marked with diagonal lines is continuously scanned.

As mentioned above, data with an ADRC encoding compression rate of 2 is recorded on the tracks located at these tape edges, so it is possible to ensure that the restored data obtained during high-speed replay is of high quality with low quantization distortion. Become. For tracks located at the tape edge, the track length allocated to one frame is doubled, so the number of screens during high-speed playback becomes 〃.
Since this is not normal playback, this is not a problem. In addition, in a vertical track row with a track width W, the number of frames that can be recorded on each disc is reduced, but in terms of the overall recording time,
Less impact. Rather, even during normal playback, a frame of high-quality restored data appears every predetermined number of frames, so
The playback quality can be improved to some extent.

d5 Modification This invention can also be applied to ADRC of three-dimensional blocks. For example, when a three-dimensional block is composed of two two-dimensional regions belonging to two frames, the number of pixels in an l block is doubled. Also, ADRC of 3D block
In order to increase the compression rate, the presence or absence of movement is determined between two two-dimensional areas, and if there is movement, the pixel data of the two two-dimensional areas, that is, the code of all pixel data in the block, is determined. When there is no movement, the pixel data of one two-dimensional area is encoded. Further, a background memory is provided, a match or a mismatch is determined with the background memory, and the background memory is updated when all frames of data in the block match and the data in the block differs from the data in the background memory. Even when using a method of ADRC encoding only the data of mismatched frames, the present invention also provides the following advantages:
Applicable. As data stored in this background memory, data with a low compression rate located at the edge of the tape may be used to provide high quality static portions that require high resolution and low noise.

Further, the present invention can be applied to cases where variable length ADRC is performed using linear quantization to keep the maximum distortion constant, and cases where ADRC is performed after subsampling to increase the compression ratio.

〔Effect of the invention〕

According to this invention, for example, data that has been highly efficiently encoded and has a lower compression rate than data recorded on other tracks is recorded on the tape edge track that is scanned during high-speed playback. Good playback image quality can be achieved during high-speed playback.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an ADRC encoder according to an embodiment of the present invention, FIGS. 2 and 3 are route diagrams for explaining the blocks, FIG. 4 is a block diagram of the ADRC decoder, and FIG. 5 6 is a perspective view of a drum mechanism of a rotary head type VTR to which this invention can be applied, and FIG. 7 is a recording pattern of a rotary head type VTR to which this invention can be applied. It is a route map shown. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2-block conversion circuit, 3: Maximum value detection circuit, 4: Minimum value detection circuit, 6.
7: Subtraction circuit, 9A, 9B: Quantization circuit, 10: Buffering circuit. Agent Patent Attorney Tadashi Sugiura Tomoyu 5L≧Z1 Town resident at Taibi,

Claims (1)

[Claims] A plurality of tracks of a predetermined length are sequentially formed from one tape edge to the other tape edge, and then a plurality of tracks of a predetermined length are formed from the other tape edge to the one tape edge. In a digital VTR that performs recording in which an operation in which tracks are sequentially formed is repeated, means for encoding a digital video signal with a high-efficiency code at a first compression rate; means for encoding the high-efficiency code at a second compression rate approximately equal to the second compression rate; A digital VT characterized in that recorded data processed at the compression rate is recorded, and recorded data processed at the first compression rate is recorded in other tracks that are not located at the tape edge.
R.