JP3304415B2 - Decoding device for block transform code - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block conversion code decoding apparatus for compressing a data amount by dividing a digital image signal into small blocks and processing the divided blocks.
In particular, the present invention relates to a decoding device that can improve the accuracy of estimation when an important word is an error.

[0002]

2. Description of the Related Art When a digital video signal is recorded on a recording medium such as a magnetic tape, the amount of information is large. Therefore, in order to achieve a transmission rate that can be recorded / reproduced, the digital video signal is encoded by a high efficiency encoding. Is usually compressed. ADRC and DCT (Discrete Cosine Trunking), which divide a digital video signal into a number of small blocks and perform encoding processing for each block, are performed as high efficiency coding.
ansform) are known. ADRC can be used, for example, as described in Japanese Patent Application Laid-Open No.
This is a high-efficiency coding that obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a dimensional block, and performs encoding adapted to the dynamic range.

The coded outputs obtained by block transform coding do not have equal importance. In the ADRC, if the dynamic range information is not known on the reproduction side, decoding of all the pixels in the block becomes impossible. Therefore, the dynamic range information detected for each block is more important than the code signal for each pixel. high. In the case of DCT, D
In the coefficient data generated by CT, the DC component has a higher importance than the AC component, and among the AC component data, a lower-order component has a higher importance than a higher-order component. In block coding in which the average value of a block and the difference between the pixel value and the average value are vector-quantized, the average value has a high importance. These encoded outputs with high importance are referred to as important words.

[0004]

In a digital VTR using ADRC, even if an important word is an error, all encoded outputs are decoded by using the value of the important word, or a block in which the important word is erroneous is replaced with an error block. In order to correct the error block with the surrounding decoded data. Regardless of the process, the block whose key word is an error is
There is a problem that block-shaped distortion is caused and deterioration of a restored image is conspicuous. Therefore, it is conceivable to estimate the error of the important word by a statistical method based on the spatial correlation between the peripheral block and the block of interest, but the estimation accuracy may be low depending on the picture. In the case of DCT, it is also possible to modify an important word using spatial correlation, but there is a similar problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a block transform code decoding apparatus capable of estimating an important word with high accuracy when the important word is an error, thereby suppressing deterioration of a restored image. It is in.

[0006]

According to a first aspect of the present invention, a digital image signal composed of a plurality of pixels is ADRC- encoded for compressing the amount of transmission information for each block composed of a plurality of spatially adjacent pixels. A block conversion code decoding device that decodes each pixel data from transmission data including data of dynamic range information with high importance for decoding and encoded values of pixels that are relatively unimportant generated by Error in dynamic range information
Error of the dynamic range information
The means for modifying and the coded value of the block of interest are all
If there is no error, the encoded value of this block of interest is
The maximum value is detected, and the detected maximum value is obtained by coding bit n.
When it is smaller than the maximum value that can be expressed (2 ⁿ -1)
The dynamic range information data at the maximum detection value.
And the transmission data is supplied, and the correct dynamic range information is replaced or replaced for each block .
Using the dynamic range information, decrypt the encoded data
It consisting of be because of the decoding means is a decoder of a block transform coding, characterized in.

According to a second aspect of the present invention, a digital image signal composed of a plurality of pixels is generated by performing block coding for compressing a transmission information amount for each block composed of a plurality of spatially adjacent pixels. the high importance for decoding
In a block transform code decoding apparatus for decoding each pixel data from transmission data including data No. 1 and second data relatively insignificant, when the first data is an error
First, regarding a block of interest in which the first data is an error,
The difference between two adjacent encoded values in the block of interest,
Two encodings in the block around the block of interest
To refer to the ratio of the difference between a value and the corresponding two encoded values
Therefore, is the data used to modify the first data
A determining means for determining whether the output signal of the determination means
To correct errors in the first data based on the
Using the correcting means and the error-corrected first data
And a decoding means for decoding the coded data .

According to a sixth aspect of the present invention, a digital image signal composed of a plurality of pixels is generated by performing block coding for compressing a transmission information amount for each block composed of a plurality of spatially adjacent pixels. In a block transform code decoding device that decodes each pixel data from transmission data including first data having high importance for decoding and second data having relatively low importance, the first data may have an error. If
First, regarding a block of interest in which the first data is an error,
The coded value in the block of interest and the surroundings of the block of interest.
Correlation between the encoded value and the corresponding decoded value in the block
By calculating the coefficient and referring to the correlation coefficient, the first
Determine if the data is used to modify the data
And determination means for, based on the output signal of the determination unit
Correction means for correcting an error in the first data
And encoding using the error-corrected first data
A block transform code decoding apparatus, comprising: decoding means for decoding data .

[0009]

[0010]

When the block of interest is in error, an important word relating to the block of interest is estimated by a statistical method using the encoded value of the block of interest and the boundary data (decoded value) of its surrounding blocks. The data used for this estimation is limited to only non-error data. This improves the accuracy of the estimation. In addition, an important word is estimated using data having a strong correlation with the block of interest instead of an error. Furthermore, in the case of ADRC, when the maximum value of the coded value xi of the block of interest is smaller than 2 ⁿ −1, the maximum value DR ′ of the coded value is the dynamic range. ´
Is replaced by

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing section of a digital VTR according to the present invention will be described. FIG. 1 shows the configuration on the recording side as a whole. A / D converters 1a and 1b convert a luminance signal Y and color difference signals U and V formed from a broadcast signal or an image signal of a color video camera into (4:
2: 2) is converted to a component digital signal. Output signals of A / D converters 1a and 1b are supplied to blocking circuits 2a and 2b, and the order of data is converted into the order of blocks. Blocking circuits 2a and 2
b is provided for a block coding circuit provided in the signal processing circuits 3a and 3b at the subsequent stage. The effective area of the screen of one field or one frame is (4 ×
4) The image is divided into blocks each having a size of pixel, (8 × 8) pixel, or the like. A blanking area exists around the effective area.

Signal processing circuits 3a and 3b to which output signals of blocking circuits 2a and 2b are supplied include ADR
It performs block transform coding such as C and DCT.
FIG. 3 shows an example of an ADRC encoder. Output signals of the blocking circuits 2a and 2b are supplied to a dynamic range DR and minimum value detection circuit 8 and a delay circuit 9. The detection circuit 8 determines the dynamic range DR of the block.
And the minimum value MIN are detected. The delay circuit 9 has a maximum value M
The data is delayed for the time to detect AX and the minimum value MIN.

In the subtraction circuit 10, the minimum value MIN is subtracted from the video data from the delay circuit 9, and video data from which the minimum value has been removed is obtained from the subtraction circuit 10. The dynamic range DR is supplied to the division circuit 11, and in the case of the 4-bit fixed-length ADRC, the dynamic range DR
Is 1/16. A quantization step Δ is obtained from the division circuit 11. The output data of the subtraction circuit 10 and the quantization step Δ are supplied to the quantization circuit 12.

A 4-bit code signal BP smaller than the original number of bits (8 bits) is obtained from the quantization circuit 12.
The quantization circuit 12 performs quantization adapted to the dynamic range DR. That is, in the quantization step Δ, the video data from which the minimum value has been removed is divided, and a value obtained by rounding down the quotient to an integer is used as the code signal BP. The quantization circuit 12 can be constituted by a division circuit or a ROM. By encoding the luminance signal Y into 4 bits and encoding the color difference signal U / V into 3 bits, for example, a recording data rate of 80 Mbps can be achieved.

The dynamic range DR, the minimum value MIN, and the code signal BP are supplied to a shuffling circuit 4, and shuffling is performed for each ADRC block. Shuffling is a process of rearranging coded outputs so as to change the arrangement of ADRC blocks within one frame. The output signal of the shuffling circuit 4 is supplied to the parity adding circuit 5.

The parity adding circuit 5 generates an error correction code, for example, a parity of a product code. The output signal of the parity addition circuit 5 is supplied to a synchronization signal and ID signal addition circuit 6, and the synchronization signal and the ID signal are added to data of a fixed length. Synchronization signal and ID signal addition circuit 6
Is supplied to the channel encoding circuit 7. Although not shown, the recording data from the channel encoding circuit 7 is supplied to a rotary head via a recording amplifier and a rotary transformer, and is recorded on a magnetic tape.

Next, the configuration of the reproducing side will be described with reference to FIG. Reproduction data from the rotary head is supplied to a channel decoding circuit 21 via a rotary transformer (not shown) and a reproduction amplifier, and the channel decoding circuit 21 demodulates channel coding. An output signal of the channel decoding circuit 21 is supplied to a TBC (time axis correction circuit) / synchronization and ID extraction circuit 22. Circuit 22
In, the time axis fluctuation component of the reproduction signal is removed, and the synchronization signal and the ID signal are extracted.

The reproduced data from the TBC / synchronization and ID extraction circuit 22 is supplied to an ECC circuit 23, where error correction using a product code is performed. The data after the error correction processing of the ECC circuit 23 is supplied to the deshuffling circuit 24. The deshuffling circuit 24 restores the arrangement of the ADRC blocks in one frame, contrary to the shuffling circuit 4 on the recording side. The output signal of the deshuffling circuit 24 is supplied to the signal processing circuits 25a and 25b.

The signal processing circuit 25a performs block decoding and error correction on the luminance signal Y, and the signal processing circuit 25b performs block decoding and error correction on the chrominance signal U / V. Error correction processing is EC
This is performed with reference to an error flag generated from the C circuit 23 and processed as described later. Block decoding and error correction include ADRC decoding of a block in which an important word (DR, MIN) is not error, modification of an important word in error, block decoding using the modified important word, and decoding of decoded pixel data. In the process, the processing for correcting the error data is performed.

The decoded luminance signal and chrominance signal from the signal processing circuits 25a and 25b are supplied to block decomposition circuits 26a and 26b, respectively. Block decomposition circuit 26a
And 26b are transmitting-side blocking circuits 2a and 2b
Conversely to b, the decoded data in block order is converted to raster scan order. Block decomposition circuits 26a and 26b
Are output from the D / A converters 27a and 27
b, and an analog reproduced luminance signal Y and a reproduced color difference signal U / V are obtained.

FIG. 4 shows an example of an ADRC decoding circuit included in the signal processing circuits 25a and 25b. The dynamic range DR and the code signal BP separated from the reproduction data are supplied to the decoder 28. The decoded output of the decoder 28 is supplied to the adder 30 and added to the minimum value MIN passed through the delay circuit 29. The decoded value Li of each pixel is obtained from the adder 30. This decoded value Li is represented by the following equation.

[0022] Li = ^{[(DR / (2 4 -1)} ) × Qi + MIN + 0.
5] = ^{[(DR / (2 4 -1)} ) × Qi + 0.5 ] + MIN

Here, Qi is an encoded value of the pixel of the code signal BP, and [] is a Gaussian symbol. In the above formula,
Are realized by the decoder 28 (for example, ROM),
The addition of the minimum value MIN is performed by the adder 30. When an important word is an error, AD using the modified important word is used.
RC decoding is performed.

After this decoding circuit, an error correction circuit for each pixel is provided. This error correction circuit forms an average value of four correct decoded data at the top, bottom, left and right of the pixel data to be corrected, and replaces the error data with this average value. If the peripheral decoded data is erroneous, interpolation using the two right and left decoded data is performed. Further, when the horizontal interpolation cannot be performed due to an error, the vertical interpolation using the upper and lower two pieces of decoded data is performed. In addition, when interpolation in the vertical direction cannot be performed, a pre-hold for holding decoded data of a pixel before the same line is performed. Note that a decoded value located in an oblique direction may also be used.

FIG. 5 shows an example of a decoding device included in the signal processing circuits 25a and 25b. In FIG. 5, 31
Indicates a first ADRC decoder, and 32 indicates a delay circuit. As described above, the reproduced data that has been reproduced from the magnetic tape, the channel code has been decoded, and the TBC (time axis correction), frame decomposition and error correction have been performed are input to the decoder 31 and the delay circuit 32 via the input switch S1. Supplied to one of the The reproduction data includes encoded data (code signal) of each pixel, a dynamic range DR for each block, and a minimum value MIN. The reproduced data also includes an error flag indicating whether or not there is an error for each sample of the code signal. Decoder 31
An output switch S2 is provided on the output side of the delay line 32. When the present invention is applied to the (4: 2: 2) component digital signal, the configuration of FIG. 5 is provided for the luminance signal and the color difference signal, respectively.

EF1 is an error flag relating to the dynamic range DR and the minimum value MIN, which are important words. The error flag EF1 has information on the presence or absence of an error regarding each of DR and MIN. For example, it is “1” when there is an error, and “0” when there is no error. The error flag EF1 is set to the delay circuit 33
Supplied to Delay circuits 32 and 33 have a delay amount corresponding to the time required for the decoding operation of ADRC decoder 31. The input switch S1 is controlled by the input error flag EF1, and the output switch S2 is controlled by the delay error flag EF2.

That is, by EF1 and EF2,
When the key word is not an error, the input switch S1 and the output switch S2 are connected to the ADRC decoder 3
If you select one side and conversely the key word is error,
The input switch S1 and the output switch S2 are the delay circuit 3
Select two sides. As a result, from the output switch S2,
A decoded output of a block in which an important word has no error and an encoded output of a block in which an important word has an error are extracted.
The output of the output switch S2 is the memory 34 and the delay circuit 3
5 is supplied. In this implementation example, the effective region of one frame (4 × 4) are divided into blocks of size of the pixel.

The memory 34 is provided for extracting a code signal of a target block to be decoded and decoded data around the target block. In FIG. 7, x1 to x16 are the encoded values of the block of interest BL0, and the decoded values y1 to y16 of the boundary data exist around the block of interest BL0. The decoded values y1 to y16 are the upper, lower, left and right blocks BL1, BL2, B of the block of interest BL0.
L3 and BL4 are the values decoded as described above. The encoded value xi and the decoded values y1 to y16 are supplied to the arithmetic circuit 36.

The arithmetic circuit 36 estimates an important word having an error using the coded value xi of the target block and the decoded value yi of the peripheral block. Where xi and y
Among i, those for which an error flag indicates that there is an error are not used for the estimation calculation. This prevents the accuracy of estimation from lowering. As the estimation method, estimation by the method of least squares, estimation using the maximum value and the minimum value of the surrounding data as the maximum value and the minimum value of the block of interest, and the like are possible.

The method of estimating an important word by the least square method is shown in FIG.
As shown in (1), the unknown slope Δ (quantization step) and the intercept MIN are obtained by the least square method from the above relational expression for ADRC decoding. That is, the primary straight line in FIG. 8 corresponds to the ADRC decoding equation for the block of interest, and the values distributed in the vicinity thereof are the decoded values yi.
The error between i and the linear line is minimized. In addition,
The range of the level distribution of the encoded values xi used in the least square method is called a range.

The correction of an error of an important word by the least square method will be described. First, if both the dynamic range DR and the minimum value MIN of the error Σxiyi = x1y1 + x2y2 + x3y3 + x4y4 + ··· + x16y16 Σxi = x1 + x2 + x3 + x4 + x1 + x5 + x9 + x13 + x13 + x14 + x 15 + x16 + x4 + x8 + x12 + x16 Σyi = y1 + y2 + y3 + ··· + y16 Σxi 2 = x 1 2 + x 2 2 + x 3 2 + ··· + y ₁₆ ² Δ = (16Σxiyi−Σxi · Σyi) / (16Σxi ² − (Σxi) ² ) MIN = (Σyi−Σxi · Δ) / 16

Next, when an error occurs only in the dynamic range DR Δ = (Σyi−16 · MIN) / Σxi Further, when an error occurs only in the minimum value MIN MIN = (Σyi−Σxi · DR / 2 ⁴⁾ ) / 16

The arithmetic circuit 36 generates an estimated output of the dynamic range DR and the minimum value MIN by performing the above-described arithmetic operations. The dynamic range DR from the arithmetic circuit 36 is supplied to the selector 37, and the dynamic range DR selected by the selector 37 is supplied to the correction circuit 38. The minimum value MIN is also supplied to the correction circuit 38.

The estimation of the important words performed by the arithmetic circuit 36 is a statistical method, and therefore causes a relatively large error depending on the picture. In order to improve the accuracy of the estimation, as described above, in addition to excluding the error sample from the calculation target, two processes are performed in this embodiment. One of them is a process of checking the number of errors in the encoded value xi and the decoded value yi and forming a determination signal SJ corresponding to the number of errors. Another process is that even when the coded value of the block of interest does not include any error, the maximum value of the coded value is n (coded bits, n = 4 in this example).
When the value is smaller than the maximum value that can be represented by bits, that is, when max {xi} <(2 ⁿ -1), since max {xi} directly represents the dynamic range DR, it is estimated by DR = max {xi}. This is the process of replacing the one that has been performed.

For the first process of improving accuracy, the memory 3
Error flag E of the encoded data of the block of interest from FIG.
Fx and the error flag EFy of the peripheral data are inverted and supplied to the NAND gate 39, the output of the NAND gate 39 is counted by the counter 40, and the count value N is supplied to the comparison circuit 41. Since the error flag is “1” with an error, the output of the NAND gate 39 is xi
Alternatively, when yi is an error, it becomes "1", which is counted by the counter 40. Therefore, the count value N of the counter 40 indicates the number of error samples in the 16 xi and 16 yi shown in FIG.

In the comparison circuit 41, N is compared with a threshold value THa, and a judgment signal SJ is formed. This determination signal S
J indicates whether (N> THa) or (N ≦ THa). The judgment signal SJ of (N> THa) has a large number of errors, and the accuracy of the estimation of the important word by the arithmetic circuit 36 lacks reliability. Indicates that Contrary to the number of errors, the number of non-errors may be counted.

For the second accuracy improvement processing, a maximum value detection circuit 42 for detecting the maximum value DR 'of the coded value of the target block is provided. This detection output DR 'is used as the comparison circuit 4
3 is supplied. The value of 2 ⁿ −1 (15 in this example) is supplied to the comparison circuit 43 as a reference value, and the comparison output is supplied to the selector 37 as a control signal thereof. The selector 37 is supplied with the dynamic range DR estimated as described above from the arithmetic circuit 36 and the detection output DR ′ from the detection circuit 42. The comparison circuit 43 compares the detection output DR ′ with the value of 2 ⁿ −1, and when DR ′ is 2 ⁿ −
When the value is smaller than 1, the selector 37 generates a comparison output for controlling the selection of DR 'as a dynamic range. The output of the selector 37 is supplied to the correction circuit 38.

An error flag EF 3 relating to an important word is supplied to the correction circuit 38 via a delay circuit 45. The important word passed through the correction circuit 38 is the second ADRC decoder 4
4 is supplied. Further, the determination signal SJ from the comparison circuit 41 and the code signal passed through the delay circuit 35 are ADRC
The data is supplied to the decoder 44. This ADRC decoder 44
, Decoded data DEC1 of each pixel is obtained. The decoded data DEC1 is supplied to one input terminal of the switch circuit S3. The output of the delay circuit 35 is supplied to the other input terminal of the switch circuit S3 via the delay circuit 46.

The switch circuit S3 is controlled by an important word error flag EF3, from which a decoded output DEC2 is extracted. The output of the delay circuit 35 is the output of the output switch S2, which is data in which the decoded output of the ADRC decoder 31 for the block whose important word is not error and the encoded output of the block for the error block are mixed. The switch circuit S3 replaces the encoded output of the block in which the important word has an error with the decoded output from the ADRC decoder 44. Further, the other decoded output DEC1 is
The decoded output is always obtained using the estimated key words. Although not shown, each of the decoded outputs DEC1 and DEC2 undergoes processing such as error correction for correcting decoded data having an error, block decomposition, and the like in the next stage.

When the determination signal SJ indicates that the reliability of the important word estimated by the arithmetic circuit 36 is low, the ADRC decoder 44 does not clear the error flag and does not perform the decoding operation. Saving of the error flag means that error data is corrected by a subsequent error correction circuit. When the reliability is high, a decoding operation using the estimated important word is performed, and the error flag is cleared.

The correction circuit 38 is provided to further improve the accuracy of the estimation of important words, and has a configuration shown in FIG. 51 subtracts the correction amount C formed as described later from DR, DR 'or MIN,
This is a correction circuit for performing correction. The addition circuit 52 adds the values of the two important words, and the added output is supplied to the subtraction circuit 53, and 255 is subtracted from the addition result. Subtraction circuit 53
Is supplied to the correction value generation circuit 54 and the comparison circuit 55.

The correction circuit 8 utilizes that the sum of the dynamic range and the minimum value obtained by the addition circuit 52 should be 255 or less in the case of 8-bit quantization. The subtraction result SA obtained by subtracting 255 from the output of the adder circuit 52 is compared with a threshold value THb (for example, 0 data) by the comparison circuit 55, and the comparison circuit 55 detects that the subtraction result SA is 0 or less. As described above, the correction value generation circuit 54 generates the correction value C only when the subtraction result SA is 0 or less. The correction value generation circuit 54 is provided with an error flag EF3 indicating the presence or absence of an important word error.

In the correction circuit 8, the correction value generation circuit 5
With the correction value C generated by 1, the input important word is corrected as follows. When both DR and MIN are errors, C = (MIN + DR (or DR ', the same applies hereinafter) -255) / 2, and DR-C and MIN-C are corrected. If only DR is in error, C = M
IN + DR-255, corrected by DR-C,
No correction for MIN is required. If only MIN is in error, then C = MIN + DR-255 and DR
The correction is performed at −C, and the correction for DR is unnecessary. If both DR and MIN are correct, (DR
+ MIN) -255 ≦ 0 is normally satisfied, and no correction is made for the important word (C = 0).

In the above-described embodiment, non-error data is used as data used for estimating an important word by the least square method. The key word can be estimated by the method of least squares based on the assumption that the decoded value of the block of interest in which the key word has an error is equal to the decoded value of non-error boundary data of a peripheral block. Therefore, when the pixel data of the peripheral block and the pixel data of the block of interest do not originally have a correlation, the result of estimation based on the assumption that there is a correlation greatly differs from the true value. Therefore, the decoded values at the boundaries of the peripheral blocks used for estimating the important words are limited to those having a relatively large correlation with the encoded value of the target block. In this way, it is possible to improve the accuracy of estimating an important word.

Several methods for examining the degree of correlation are proposed. First, a method using a correlation coefficient will be described. The correlation coefficient γ is calculated by the following equation.

[0046]

(Equation 1)

Here, as shown in FIG. 9A, the encoded value around the target block BL0 and the upper adjacent block BL0
One correlation coefficient is obtained with respect to the decoded value at the boundary of 1, and similarly, the correlation coefficient between the encoded value around the target block and the adjacent blocks BL2, BL3, and BL4 is calculated. When calculating the correlation coefficient, an encoded value or a decoded value that is in error is excluded. Therefore, a total of four correlation coefficients are obtained.

Then, regarding the obtained correlation coefficient γ,
The condition of Expression (1) is introduced, and only a set satisfying this condition is used. γ ≧ α (α: threshold value of −1 ≦ α ≦ 1) (1) For example, the correlation coefficient obtained from the set including the target block BL0 and the boundary data of the adjacent block BL4 is represented by Expression (1). When the condition is not satisfied, the data in the area surrounded by FIG. 9B is used for estimation. By estimating only data having a strong correlation in this way, the accuracy of the estimation can be improved.

The target block BL0 and the peripheral block BL
If all of the four units composed of the boundary data of 1, BL2, BL3, and BL4 do not satisfy the condition of Expression (1), the keyword is estimated using all non-error data. .

ADRC is normalization for removing the minimum value MIN and requantization after normalization.
The same level change characteristics as the original value are preserved. Therefore, the degree of correlation can be determined from the correlation coefficient between the coded value of the target block and the decoded value of the boundary.

In order to increase the estimation accuracy of the method using the least squares method, preferably, the condition of the following equation (2) is used in addition to the equation (1). R ≧ β (threshold value of β = 0 ≦ β) (2) where R is one peripheral block (BL1, BL2,
BL3, BL4) is the difference between the maximum value and the minimum value of the boundary data. Similarly to the correlation coefficient, it is determined whether Equation (2) holds for four sets of boundary data.

This is based on the fact that the use of data having a wide range (existence range) shown in FIG. In other words, if the range is narrow,
The accuracy of the slope of the approximate straight line decreases, and the accuracy of estimating the dynamic range and the minimum value decreases. Equation (1) above
An important word is estimated using data that satisfies both the conditions of Expression (2) and Expression (2).

The block of interest BL0 and the peripheral block BL
If all of the four units composed of the boundary data of 1, BL2, BL3, and BL4 do not satisfy the conditions of Expressions (1) and (2), similar to the above, non-error data The key word is estimated using all of.

A method of checking the degree of correlation without using a correlation coefficient will be described below. In FIG. 10, BL
0 is the block of interest, and x1 to x16 are the block of interest B
This is the coded value in L0. x1 'to x16' are encoded values corresponding to the boundary decoded values y1 to y16. In the case of ADRC, the encoded value holds the original pixel value,
The degree of correlation is determined using the encoded value of the boundary between the block of interest and the surrounding block.

Looking at the upper boundary of the block of interest,
If the way in which the encoded values x1 to x4 and x1 'to x4' change are very similar, it is determined that the correlation is strong. Therefore, the ratio of the difference between adjacent data is determined. For example, c1 = (x1−x2) / (x1′−x2 ′) (3) As c1 is closer to 1, the manner of change is similar.
However, when the denominator is 0, c1 = 1 only when the numerator is 0.
Otherwise, it is undefined.

A threshold value T is determined for the obtained difference ratio c1.
h1 is set. That is, (1-c1) ABS <Th1 (4) () ABS means an absolute value. When the equation (4) is satisfied, the sample used to calculate the difference ratio and the corresponding decoded value (within the peripheral block) are used for estimation. If this is not the case, the decoded value corresponding to the sample is not used for estimation.

The difference ratio ci is obtained in the same manner as described above, shifting one sample at a time. With respect to the ratio ci, it is checked whether or not Expression (4) is satisfied. That is, c2 = (x2-x3) / (x2'-x3 ') (1-c2) ABS <Th1 c3 = (x3-x4) / (x3'-x4') (1-c3) ABS <Th1 ...・ ・

If the above condition is satisfied and the other case does not occur simultaneously with respect to a certain sample, the sample is used for estimating an important word. In this way, an important word can be estimated using data having a stronger correlation, and the estimation accuracy can be improved.

FIG. 11 shows a decoding apparatus in which data having a relatively strong correlation is used. In FIG. 11, reference numeral 61 denotes an input terminal of a signal reproduced by the rotary head.
Reference numeral 2 denotes a reproduction amplifier, a channel decoding circuit, and an error correction circuit. In FIG. 11, the data path is indicated by a solid line, and the error flag path is indicated by a broken line.

The error-corrected data and the error flag are supplied to the ADRC decoding circuit 63 and the arithmetic circuit 68, and the decoding is performed on the block in which the important words (DR, MIN) are not errors. The output of the ADRC decoding circuit 63 and the error flag are supplied to the important word estimation circuit 64.
This output is a decoded output for a block in which the keyword is correct, and is a coded value for a block in which the keyword is in error. The important word estimating circuit 64 estimates important words by processing non-error data by the least square method.

ADRC connected to key word estimation circuit 64
The decoding circuit 65 performs decoding using the estimated important word. However, the decoded output of the block already decoded by the ADRC decoding circuit 63 is guided to the output terminal 66 as it is. The output terminal 67 is an output terminal for an error flag.

The arithmetic circuit 68 calculates the difference ratio ci for the block of interest to be decoded, and calculates (1-ci) A
Calculate BS. The output of the arithmetic circuit 68 is supplied to the determination circuit 69, and is compared with the threshold value Th1, to determine whether the condition of Expression (4) is satisfied. This determination result is supplied to the important word estimation circuit 64 and the counter 70. The important word estimating circuit 64 estimates an important word using data that satisfies the condition of Expression (4) instead of an error.

The counter 70 counts peripheral data that satisfies the condition of equation (4). This count value is supplied to the determination circuit 71 and compared with the threshold value Th2, and a determination output according to the comparison result is generated. This judgment output is A
It is supplied to the DRC decoding circuit 65. Count value is threshold T
When it is smaller than h2, it is determined that the estimation accuracy is low, and the ADRC decoding circuit 65 is prohibited from using the estimated important word. As a result, all the pixels of the block are subjected to the correction of the error correction circuit at the subsequent stage.

In the above embodiment, ADRC is used as block coding, but block coding such as DCT may be used.

[0065]

According to the present invention, for a block in which an important word is erroneous, an important word is estimated using an error-free decoded value existing around the block. Can be improved. Therefore, a good restored image can be obtained without the accuracy of the estimation being affected by the pattern.

According to the present invention, the degree of correlation between the boundary data of the block and the peripheral block is determined as the data used for estimation, and data having a strong correlation is selectively used. it can.

[Brief description of the drawings]

FIG. 1 shows a digital V to which the present invention can be applied.
It is a block diagram of an example of a recording system of TR.

FIG. 2 shows a digital V to which the present invention can be applied.
It is a block diagram of an example of the reproduction | regeneration system of TR.

FIG. 3 is a block diagram showing an encoding circuit of ADRC.

FIG. 4 is a block diagram showing a decoding circuit of ADRC.

FIG. 5 is a block diagram of an example of a decoding circuit according to the present invention.

FIG. 6 is a block diagram illustrating an example of a correction circuit in the decoding circuit.

FIG. 7 is a schematic diagram for explaining data used for an important word estimation process.

FIG. 8 is a schematic diagram illustrating an important word estimation process.

FIG. 9 is a schematic diagram for explaining an important word estimation process.

FIG. 10 is a schematic diagram for describing data used in another example of the important word estimation process.

FIG. 11 is a block diagram of another example of the decoding circuit according to the present invention.

[Explanation of symbols]

31, 44 ADRC decoder 34 Memory for extracting peripheral data 40 Counter for counting the number of errors in data used for estimation processing 42 Maximum value detection circuit for peripheral data

Continuation of the front page (72) Inventor Atsushi Yada 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Ken Satoshi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sonny Inside (72) Inventor Akemi Noda 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-63-257390 (JP, A) JP-A-2-219387 ( JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N ^7/ 24-7/68

Claims (6)

(57) [Claims] An important element for decoding, which is generated by performing ADRC encoding on a digital image signal composed of a plurality of pixels for each block composed of a plurality of pixels which are spatially adjacent to each other to compress the amount of transmission information. In a block conversion code decoding device for decoding each pixel data from transmission data including data of a high degree of dynamic range information and an encoded value of each pixel that is relatively insignificant, the data of the dynamic range information may include an error. Means for correcting an error in the data of the dynamic range information, and in the case where the encoded values of the block of interest are not all errors,
The maximum value of the coded value of the target block is detected, and when the detected maximum value is smaller than the maximum value (2 ⁿ −1) that can be represented by the coded bit n, the dynamic range is determined by the detected maximum value. Means for replacing information data, and decoding means for decoding the coded data by using the correct dynamic range information or the replaced dynamic range information for each of the blocks supplied with the transmission data. An apparatus for decoding a block transform code, characterized in that: 2. An important part for decoding, which is generated by subjecting a digital image signal composed of a plurality of pixels to block encoding for compressing the amount of transmission information for each block composed of a plurality of spatially adjacent pixels. First data with high degree,
In a block conversion code decoding apparatus for decoding each pixel data from transmission data including second data that is relatively insignificant, when the first data is an error, the first data is an error. For the block, refer to the ratio of the difference between two adjacent encoded values in the block of interest and the difference between the two encoded values and the corresponding two encoded values in the peripheral blocks of the block of interest. And determining means for determining whether the data is used for correcting the first data, and correcting errors in the first data based on an output signal of the determining means. A block conversion code decoding apparatus, comprising: a correction unit; and a decoding unit for decoding the encoded data using the first data with the error corrected. 3. The method according to claim 1, wherein the determining unit determines a difference between two adjacent encoded values in the target block and two encoded values corresponding to the two encoded values in a peripheral block of the target block. Depending on whether the value difference ratio is close to 1,
3. The apparatus according to claim 2, wherein it is determined whether or not the data is used for modifying the first data. 4. The modification means estimates the first data by a least squares method using a coded value in the block of interest and a decoded value of the peripheral block near the boundary of the block of interest. 3. The decoding apparatus according to claim 2, wherein: 5. The method according to claim 1, wherein the ratio of the difference is (0/0).
= 1), wherein the block transform code decoding apparatus according to claim 2 is used. 6. An important part for decoding, which is generated by subjecting a digital image signal composed of a plurality of pixels to block encoding for compressing the amount of transmission information for each block composed of a plurality of spatially adjacent pixels. First data with high degree,
In a block conversion code decoding apparatus for decoding each pixel data from transmission data including second data that is relatively insignificant, when the first data is an error, the first data is an error. With respect to the block, a correlation coefficient between the encoded value in the block of interest and a decoded value corresponding to the encoded value in the peripheral block of the block of interest is calculated, and by referring to the correlation coefficient, Determining means for determining whether or not the data is used for correcting the first data; and correcting means for correcting an error in the first data based on an output signal of the determining means. A decoding means for decoding the encoded data by using the first data with the error corrected, wherein the decoding unit decodes the encoded data.