JP3158603B2 - Digital image signal transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus for digital image signals using, for example, DCT as high-efficiency coding, and more particularly to a frame decomposition circuit for decomposing transmission data having a frame structure into a plurality of data.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head, for example, is known. Because of the large amount of digital video signal information,
High-efficiency coding for compressing the transmission data amount is often adopted. Among various high efficiency codings, DC
The practical use of T (Discrete Cosine Transform) is in progress.

[0003] DCT converts an image of one frame into, for example, (8
.Times.8), and the block is subjected to cosine transform, which is a type of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to a variable length coding process such as a run length code and a Huffman code. At the time of transmission, in order to facilitate data processing on the reproducing side, framing for converting a plurality of data such as a code signal and an ID signal, which are coded outputs, into a frame structure is performed. As this frame structure, a configuration of a sync block to which a block synchronization signal is added for each data of a fixed length is adopted. On the reproduction side, frame decomposition is performed to separate the frame structure into a plurality of data.

A digital VTR using a magnetic tape,
In a disk recording device or the like using a disk-shaped recording medium, one field or one frame of video data is usually recorded on one or two or more integer tracks. However, when a variable length output is formed as in the above-described DCT, the data amount in one frame period varies. Therefore, a buffering process for reducing the data amount in one frame period to a target value or less is required.

As an example, the amount of data in a predetermined period (referred to as a buffering unit) shorter than one frame is controlled,
As a result, a buffering process for reducing the data amount to a target value or less even in the entire one frame period has been proposed. The buffering process is a process of requantizing the coefficient data of the alternating current generated by the DCT at an appropriate quantization step to suppress the transmission data amount to a target value or less. A quantization step or a code of a quantization number indicating the quantization step is inserted into the transmission data together with the encoded data. This is an example of an important word.

[0006]

Conventionally, when an important word is included in each sync block of reproduced data and an error occurs in the quantization number, even if the code signal of the sync block is not an error, the error occurs. Since the quantization step at the time of recording is unknown, this code signal cannot be used. The quantization number is added to each sync block generated in a predetermined period, and the same data is used among a plurality of sync blocks.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital image signal transmitting apparatus which can effectively use coded data which is not error even when an important word is an error in reproduced data. It is in.

[0008]

The present invention provides a synchronization signal,
In a digital image signal transmitting apparatus in which a sync block in which an encoded word of image information and an important word necessary for decoding the encoded output are arranged receives continuous transmission data, the important word is a predetermined sync block. During the period
An important word detection / hold circuit for detecting and holding a plurality of important words contained in the received data, which are correct within a predetermined period and included in the received data, and an encoded output are provided. A digital image signal transmission device, comprising: a buffer memory; a data extraction circuit for associating the detected correct important word with an encoded output from the buffer memory and outputting the data to a decoding means at a subsequent stage. is there.

[0009]

An error is detected for an important word of each sync block of the reproduction data. The important word is common between a plurality of consecutive sync blocks. After waiting for a correct one of the common important words to be detected and held, the important word and a code signal as an encoded output are output in association with each other. Therefore, even if the key word is an error, when the code signal is not an error, the quality of the reproduced image can be improved by effectively using the code signal.

[0010]

An embodiment of the present invention will be described below with reference to the drawings. To understand the present invention, the configuration of a video data processing circuit provided on the recording side of the digital VTR will be described first. In FIG. 1, digitized video data is supplied to an input terminal 1. This video data is supplied to the blocking circuit 2. In the blocking circuit 2, the video data in the raster scanning order is converted into, for example, (8 × 8) two-dimensional block structure data.

The output of the blocking circuit 2 is supplied to a DCT (cosine transform) circuit 3. (8 × 8) coefficient data generated by the DCT circuit 3 (data of one DC component and 63
(Comprising data of the number of ACs) is supplied to the quantization circuit 5 via the delay circuit 4. For example, 64 coefficient data in one block are transmitted in order from the AC component having a lower order to the AC component having a higher order in a zigzag scanning order, with the DC component at the head. Also, this coefficient data is used by the estimator 6
Is also supplied. The delay circuit 4 has a delay amount corresponding to the time required for the estimator 6 to determine an appropriate quantization step.

In the quantization circuit 5, the DC component in the coefficient data is not requantized, but the AC component is requantized. That is, the coefficient data for the AC is divided by an appropriate quantization step, and the quotient is converted to an integer. This quantization step is determined by the quantization number from the estimator 6. In the case of a digital VTR, since processing such as editing is performed in units of fields or frames, the amount of generated data per field or frame needs to be equal to or less than a target value. Since the amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded, a buffering process for reducing the amount of data generated in a buffering unit shorter than one field or one frame period to a target value or less. Is made. The reason for shortening the buffering unit is to simplify the buffering circuit, for example, by reducing the memory capacity for buffering. In this example, 15 macroblocks are set as a buffering unit.

The output of the quantization circuit 5 is a variable length coding circuit 7
, And run-length coding, Huffman coding, and the like are performed. For example, two-dimensional Huffman coding is employed in which a zero run, which is the number of consecutive “0” s of coefficient data of a code, and the value of coefficient data are given to a Huffman table to generate a variable length code (encoded output). The DCT code from the variable length coding circuit 7 is supplied to a packing circuit 8 and D is divided into data areas of sync blocks by byte width.
The CT code is formed by the packing circuit 8. The output of the packing circuit 8 is supplied to a parity generation circuit 9 to form a parity of the error correction code. The output of the parity generation circuit 9 is supplied to the multiplexer 10.

The output of the parity generation circuit 11 is supplied to the multiplexer 10. The quantization number QNO from the estimator 6 is supplied to the additional information (AIN) generation circuit 12, and the additional information AIN including the quantization number QNO is generated. This is subjected to error correction encoding by a parity generation circuit 11 and then supplied to a multiplexer 10 corresponding to a framing circuit. The multiplexer 10 is also supplied with a block synchronization signal SYNC. Multiplexer 10
Performs time division multiplexing of the outputs of the parity generation circuits 9 and 11 and the block synchronization signal SYNC, and generates transmission data at an output terminal 13. Although not shown, the transmission data is supplied to two rotating heads via a channel encoding circuit and a recording amplifier, and is recorded on a magnetic tape.

The estimator 6 can reduce the amount of data generated in buffering units to a target value or less, and determines a quantization step having a value as small as possible. FIG. 2 shows an example of the estimator 6. n quantization circuits 20 ₁ , 20 ₂ ,
.., 20 _n are supplied with coefficient data from the DCT circuit 3. These quantization circuit 20 ₁ to 20 _n, the quantization step Δ1 mutually different from the quantization step generator 21, Δ2, ···, Δn is supplied.

[0016] is divided by the quantization step, output which is integer are supplied to the variable length coding circuit 22 ₁ through 22 _n. These variable length encoding circuits 22 _{1 to} 22 _1
n is different from the variable length coding circuit 7 which actually generates a variable length code, and generates data of the code length of the variable length coded output. Data for this code length accumulator circuit 23 _1-23
n respectively. The accumulation circuit 23 ₁ ~ 23 _n, a reset pulse from terminal 24 is supplied. Accumulation circuit 23 ₁ ~ 23 _n is generated in the buffer unit D
The amount of the CT code is obtained. In this example, a reset pulse is generated every 15 macro blocks. Accumulation circuit 2
3 ₁ ~ 23 _n accumulator output is supplied to the determination circuit 25.

The determination circuit 25 receives a target value A from a terminal 26.
m is supplied. The output of the accumulator circuit 23 ₁ ~ 23 _n and the target value Am is compared, in a range not exceeding the target value Am, most target value Am and close accumulator output, i.e., the optimal accumulator output is determined. By this determination output, the quantization number QNO
Is determined and taken out to the output terminal 27. This quantization number QNO is supplied to the quantization circuit 5. Quantization circuit 5
Is provided with a ROM for converting a quantization number into a quantization step.

The estimator 6 is not limited to the configuration shown in FIG. 2, but may employ various configurations such as a method of sequentially performing quantization in different quantization steps. In addition, a common quantization step is not limited to the coefficient data of the AC components of all orders, and a quantization step according to the order may be used. That is, the coefficient data for the AC is divided into a plurality of groups according to the order, and a quantization step is prepared for each of the plurality of groups. When different quantization steps are used, a plurality of sets of quantization steps for a plurality of groups are prepared, quantization is performed using a plurality of sets of quantization steps, and the optimum quantization step is determined by referring to the result. It is determined.

FIG. 3 shows one sync block (SB) formed by the multiplexer 10. A block synchronization signal SY is provided at the beginning of a sync block having a continuous byte structure.
NC is located and then a quantization number QN to identify the quantization step used for buffering
In the data area after the additional information AIN, a DCT code whose data amount is controlled by buffering and a parity PT of an error correction code added for each data of the sync block are located. To position. The additional information contains the parity of the error correction code for the additional information, and if necessary, the address of the macroblock, the sync number, and the ID indicating the type of data.
Etc. are inserted.

As an error correction code, a product code is used, and Reed-Solomon code is encoded for the data in the horizontal and vertical directions. The horizontal error correction code is called an inner code, and the vertical error correction code is called an outer code. The inner code is performed on data included in the data area of one sync block, and a horizontal parity PT is generated. Some sync blocks may include only vertical parity. At the time of variable speed reproduction, data cut out as a sync block is treated as valid, and error correction using an inner code is performed.

In this example, as shown in FIG. 4, buffering is performed so that DCT codes of 15 macro blocks are arranged in the data area (shaded area) of 15 sync blocks SB1 to SB15. In other words, control is performed so that the data amount of the buffering unit (15 macroblocks) falls within the data area of the 15 sync blocks SB1 to SB15. The specific length of the data area of each sync block is defined in consideration of this point. The numerical value of 15 is merely an example. In short, the buffering is performed such that the data of the buffering unit is contained in the data area of the integer number of sync blocks.

The number of macro blocks per block is (8
× 8) is obtained by collecting a plurality of blocks of coefficient data.
For example, (Y: U: V = 4: 1:
In the case of the video data of 1), four Y blocks, one U block, and one V block at the same position in one frame
A total of six blocks including one block constitute one macro block. When the sampling frequency is 4 fsc (fsc: color subcarrier frequency), an image of one frame is (91
0 samples × 525 lines), of which the valid data is (720 samples × 480 lines). In the case of the above component system, the total number of blocks in one frame is (720 × 6/4) × 480 ÷ (8 × 8) =
8100. Therefore, 8100 ÷ 6 = 1
350 is the number of macroblocks in one frame.

Further, as shown in FIG. 5, two tracks are simultaneously formed on the magnetic tape by two closely arranged rotary heads, and ten tracks T0 to T0 are formed.
One frame of data is divided and recorded in T9. Note that the PCM audio signal is error-correction-coded,
It is recorded together with video data, or recorded in an audio data recording section provided in one track.

Since one frame is composed of 1350 macroblocks, 135 macroblocks are recorded per track. Since the buffering unit is 15 macro blocks, nine buffering units (video group 0 to video group 8) are recorded in one track as shown with respect to track T0. As described above, since the data amount of each video group is controlled to be equal to or slightly smaller than the target value Am, data of 135 macroblocks can be recorded on each track of a fixed length. At the time of variable speed reproduction, for example, when the tape speed is four times faster than at the time of recording, two rotating heads draw a scanning locus indicated by a broken line in FIG. The data is played.

FIG. 6 shows the configuration of a reproduction processing circuit of a digital VTR to which the present invention is applied. An input terminal indicated by 31 is supplied with reproduction data picked up from a magnetic tape by a rotary head and passed through a reproduction amplifier, a channel coding decoding circuit and the like. Reference numeral 32 denotes a clock extraction circuit that extracts a clock synchronized with the reproduced data, and reference numeral 33 denotes a synchronization detection circuit that detects a synchronization signal of a sync block. The clock and the reproduced synchronizing signal from these circuits 32 and 33
And various timing signals necessary for processing the reproduction data are formed.

An error correction circuit 35 provided after the synchronization detection circuit 33 detects and corrects errors in reproduced data. As described above, each error detection and correction is performed by both error correction coding for the additional information AIN and error correction coding for the variable length coded output of video data (in some cases, vertical parity of a product code). It can be carried out. This error correction circuit 35
Outputs the corrected additional information and the code signal, and outputs an error flag indicating the presence or absence of these errors. In FIG. 6, an error flag EF of the additional information is shown.
Only a is shown.

An output of the error correction circuit 35 is supplied to an input terminal of the switch circuit 36. The switch circuit 36 selects one of the output terminals a and b according to a control signal from the timing generation circuit 34. This switch circuit 36
A code signal is selectively taken out from an output terminal a of
Additional information is selectively extracted from the output terminal b. The code signal from the output terminal a is stored in the buffer memory 37.
Supplied to The buffer memory 37 stores, for example, data of 15 macroblocks in buffering units.
It has a capacity to store code signals of 5 sync blocks.

The error flag EFa is supplied to the AND gate 39 in the additional information hold circuit 38 after being inverted. The error flag EFa is one bit of “1” when an error occurs and “0” without an error. The AND gate 39 supplies the additional information A in the data from the timing generation circuit 34.
At the position (timing) of IN, a pulse signal SL that becomes “1” is supplied. Therefore, when there is an error, AN
The passage of the pulse signal SL is prohibited by the D gate 39.

The output of the AND gate 39 is used as an enable signal for the register 40. The clock from the timing generation circuit 34 is supplied to the register 40 as a clock input, and the additional information AIN from the output terminal b of the switch circuit 36 is supplied as a data input. This AN
An additional information hold circuit 38 comprising a D gate 39 and a register 40 holds only correct additional information, and when the next correct additional information comes, holds it. As the hold circuit 38, a majority logic circuit may be used.

The code signal from the buffer memory 37, the error flag EFa, and the additional information from the hold circuit 38 are supplied to a data cutout circuit 41. The code signal from the buffer memory 37, the additional information from the hold circuit 38, and the error flag are output by the data extracting circuit 41 in association with each other. More specifically, these are output from the cutout circuit 41 in synchronization. A depacking circuit 42 is provided after the data extracting circuit 41, and converts a code signal in byte units into a variable-length code. Then, the variable-length code decoder 43
For example, two-dimensional Huffman codes are decoded.

An inverse quantization circuit 44 is provided for the decoder 43.
Is connected. The inverse quantization circuit 44 is a process for forming a representative value by multiplying the code signal by a quantization step, contrary to the quantization at the time of recording. After the inverse quantization circuit 44, an error correction circuit 45 is connected. The error correction circuit 45 corrects an error that cannot be corrected and remains with correct data. For the error correction circuit 45,
The DCT inverse transform circuit 46 is connected, and pixel data is restored from the coefficient data. The reconstructed data from the DCT inverse transform circuit 46 is supplied to the block decomposition circuit 47, and is converted from the block order to the raster scan order. The error correction circuit 45 may be provided after the DCT inverse transform circuit 46.

The present invention can be applied not only to a digital VTR but also to a disk recording / reproducing apparatus, a case where digital image signals are transmitted through a communication path, and the like.

[0033]

According to the present invention, in the case where the important word is an error in the reproduced data and the code signal corresponding to the video data is a correct sync block, the correct sync block is provided in a predetermined number of subsequent sync blocks. If an important word exists,
The reproduced image can be restored by effectively using the code signal of the sync block in which the important word is in error. Therefore, it is possible to reduce deterioration of the quality of the reproduced image due to the error.

[Brief description of the drawings]

FIG. 1 is a block diagram of a recording data processing circuit of a digital VTR to which the present invention is applied.

FIG. 2 is a block diagram illustrating an example of a buffering configuration;

FIG. 3 is a schematic diagram for explaining an array of sync blocks of transmission data.

FIG. 4 is a schematic diagram illustrating a relationship between a buffering unit and a sync block.

FIG. 5 is a schematic diagram of a track pattern according to an embodiment of the present invention.

FIG. 6 is a block diagram of a reproduction data processing circuit of a digital VTR to which the present invention is applied.

[Explanation of symbols]

 31 Reproduction data input terminal 35 Error correction circuit 37 Buffer memory 41 Data extraction circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N ^7/ 24-7/68 G11B 20/18

Claims (1)

(57) [Claims] 1. Transmission of a digital image signal in which a sync signal, an encoded output of image information, and a sync block in which important words necessary for decoding the encoded output are arranged receive continuous transmission data. In the apparatus, the important word is a plurality of identical data during a predetermined sync block period.
Means for detecting and holding the important words contained in the received data, which are correct within a predetermined period, and a buffer memory to which the coded output is supplied; A digital image signal transmission device, comprising: means for associating the correct important word with the encoded output from the buffer memory and outputting the result to a decoding means at a subsequent stage.