JPS6395277U

JPS6395277U -

Info

Publication number: JPS6395277U
Application number: JP19135686U
Authority: JP
Priority date: 1986-12-12
Filing date: 1986-12-12
Publication date: 1988-06-20

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す集積回路基板
の平面図、第２図は側面図、第３図は従来の集積
回路基板の平面図、第４図は側面図、第５図は一
部の平面図である。ａ_１，ａ_２，ａ_３……下部導体、ｂ……上部導
体、ｃ_１……第１の絶縁層、ｃ_２……第２の絶縁
層、１……回路基板、イ……歪、ロ……クラツク
、ハ……滲み。 Fig. 1 is a plan view of an integrated circuit board showing an embodiment of the present invention, Fig. 2 is a side view, Fig. 3 is a plan view of a conventional integrated circuit board, Fig. 4 is a side view, and Fig. 5 is a plan view of a conventional integrated circuit board. It is a partial plan view. a ₁ , a ₂ , a ₃ ... lower conductor, b ... upper conductor, c ₁ ... first insulating layer, c ₂ ... second insulating layer, 1 ... circuit board, a ... strain, B...cratsuku, ha...smear.

Claims

[Scope of utility model registration request]

On the substrate, a first lower conductor, a second lower conductor and a third lower conductor sandwiching and facing each other so as not to be connected to the first lower conductor.
A first insulating layer is formed between the second lower conductor and the third lower conductor, the first insulating layer is overlapped with both ends thereof and covers the first lower conductor, and this insulating layer a second insulating layer is formed on the second insulating layer, and the second lower conductor and the third insulating layer are formed on the second insulating layer.
An integrated circuit board comprising: an upper conductor that is electrically connected to a lower conductor of the integrated circuit board.