JPS6392986A - Pattern development - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for developing character patterns, etc. output from a pattern generation section onto a bitmap memory.

[Prior art]

Conventionally, when developing character patterns etc. from a pattern generation section onto a bitmap memory, a master processing device generally read the pattern data from the pattern generation section (character generator) through software processing and developed it onto the bitmap memory. . However, since reading and writing to bitmap memory is generally performed in word or byte units, masking is required if the boundaries do not match the boundaries of the pattern output from the pattern generator, which slows down the expansion process. There was a problem.

〔the purpose〕

SUMMARY OF THE INVENTION An object of the present invention is to speed up the process of developing character patterns, etc. output from a pattern generation section onto a bitmap memory.

[prayer completed]

The present invention provides an address generation section and a pattern generation memory. First, the address generation section generates a boundary address of the bitmap memory, and the pattern data of the boundary area of the bitmap memory is read out and written into the corresponding area of the pattern generation memory.Then, the pattern data is output from the pattern generation section. Write the pattern data in the pattern generation memory and combine it with the pattern data in the boundary area of the bitmap memory.The address generation section generates word-by-word addresses in the bitmap memory, and converts the contents of the pattern generation memory into words. It is written to the bitmap memory in units of units.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows the relationship between the address structure of the bitmap memory and the development area of the generated pattern. 2N, and the bitmap memory has a word structure (16 bits) as seen from the CPU. In Figure 4, B
AW is the first word of bitmap memory, BAW+1
．． BAW+2°... EAW indicates the last word of one row, and BAW+LA (LA is the width of the bitmap area) indicates the word one row below BAW.

Now, if you try to develop the pattern in the pattern generation area on the bitmap memory as shown by diagonal lines, the pattern will not match the word boundaries of the bitmap memory, so after masking only the overlapping part in advance, the pattern will be generated. The present invention speeds up this processing.

FIG. 1 is an overall block diagram of an embodiment of the present invention, in which a control section 1 manages the overall control, a pattern generation section 2 generates pattern data. It consists of a pattern generation memory 3 that generates a pattern to be developed in a bitmap memory, and an address generation section 4 that generates addresses for the bitmap memory and the pattern generation memory 3.

FIG. 2 shows an example of the configuration of the address generation circuit of the address generation section 4, especially the bitmap memory.
, address register 42. It consists of selectors 43 and 44. The address generation unit 4 is also equipped with an address generation circuit for the pattern generation memory 3, but this is omitted because it may be a simple counter. FIG. 3 shows a configuration example of the pattern generation memory 3, in which a parallel-to-serial conversion circuit 31,
Serial parallel conversion circuit 32, switch circuit 33, memory 34
It becomes more. CK is a clock, and obt is a control signal corresponding to the overlay bit size, both of which are supplied from the control unit 1.

The control unit 1 receives the write start word BAW from the master CPU,
The width LA of the bitmap memory area and the overlay bit size obt are taken as parameters, of which B
AW and LA are passed to the address generation section 4, and obt is a control signal for the switch circuit 33 of the pattern generation memory 3.

The address generating section 4 first sets B and AW as they are in the address register 42 through the selector 43 and the adder 41, and reads out the data at the first location of BAW in the bitmap memory. The data is converted into serial dots by a parallel-to-serial conversion circuit 31, passes through a switch circuit 33, and is sequentially written into the memory 34 from the beginning. At this time, when the data of the overlay bit size obt is written to the memory 34, the switch circuit 33 is turned off according to the instruction from the control unit 33, so that the remaining dots are transferred to the memory 34.
Writing to 4 is prohibited. That is, only the portion of one word of BAW that is not overlaid is written.

When the capture of one word is completed, the address generator 4
selects the contents (BAW) of the address register 42 and the value LA by the selectors 43 and 44, obtains BAW+LA by the adder 41, sets this in the address register 42, and writes the data at address BAW+LA in the bitmap memory. This data to be read out is also converted into serial dots by the parallel-to-serial conversion circuit 31, and is then converted to serial dots via the switch circuit 33.
A dot of the overlay bit size is written to the next row of memory 34. below.

By adding LA to the contents of the address register 42 and repeating the same process, the part of the data at the leftmost word boundary of the bitmap memory that is not overlaid with the pattern output from the pattern generator 2 is written to the memory 34. . Similarly.

By accessing the bitmap memory as EAW, EAW+LA, . . . , data at the leftmost word boundary of the bitmap memory is written to the memory 34.

Next, when generating a pattern, the address generation unit 4 uses the memory 3
4 horizontal and vertical addresses are sequentially generated, and the serial dot generation pattern output from the pattern generating section 2 is sequentially written into the memory 34 through the switch circuit 33. At this time, the switch circuit 33 responds to instructions from the control section 1. Therefore, periods that are not overlaid are turned off. As a result, in the memory 34, the previously read bitmap memory contents remain in N areas that are not overlaid, and when this is redeployed to the bitmap memory, the bitmap memory outside the overlay boundary remains N. The N patterns held in the boundary remain as they are, and it appears as if the generated pattern has been newly written within the boundary.

When redeploying to the bitmap memory, the address generating unit 4 selects BAW and "1" with selectors 43 and 44, and selects BAW and "1" with adders 41 and 44, respectively. Address register 42. Selector 43
BAW, BAW+1, BAW+2. . . . are generated sequentially and used as the write address of the bitmap memory. On the other hand, the contents of the memory 34 are sequentially read bit-serially from the beginning, input to the serial/parallel converter circuit 32 via the switch circuit 33, and converted into data in units of one word. This data is stored in bitmap memory BAW and BA.
W+1. BAW+2. ... will be written to each address.

〔effect〕

As is clear from the above description, according to the present invention, speeding up can be achieved by providing an address generation section on the pattern generation section side and processing address calculations necessary for pattern expansion using hardware. Furthermore, when the contents of the bitmap memory are read into the pattern creation memory, only the memory contents at the boundaries are read, so speeding up is also achieved from this point of view.

[Brief explanation of the drawing]

Figure 1 is an overall block diagram of an embodiment of the present invention, Figure 2 is a detailed diagram of the address generation section, Figure 3 is a detailed diagram of the pattern generation memory, and Figure 4 is the address structure and generation of the bitmap memory. FIG. 3 is a diagram showing the relationship between pattern development areas. 1... Control section, 2... Pattern generation section. 3...Memory for pattern generation. 4...Address generation section. Figure 2 Figure 3 Figure 4 See tQ-1-

Claims (1)

[Claims] (1) In a pattern development method that develops a generated pattern into a bitmap memory, an address generation section and a pattern generation memory are provided, the address generation section generates a boundary address of the bitmap memory, and data in the boundary area is generated into a pattern. 1. A pattern development method comprising: writing a generated pattern into a memory for pattern generation, writing the generated pattern into a memory for pattern generation, and redeploying the contents of the memory for pattern generation into a bitmap memory.