JPH06161879A - Digital data processor - Google Patents

Abstract

PURPOSE:To read data stored at continuous addresses inside a DRAM at high speed and to enable arithmetic processing. CONSTITUTION:This device is provided with a DRAM 11 equipped with a high- speed page mode, CPU 12 connecting a data bus 15 to the DRAM 11, and address translation circuit 14 for generating the two kinds of addresses such as a time sharing address composed of a row address and a column address and an address composed of only the column address to the DRAM 11. The DRAM 11 provided with the high-speed page mode is operated in a page mode, and a CPU 12 reads the data stored at the continuous addresses inside the DRAM 11 without waiting time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data processing device for reading data stored in consecutive addresses in a DRAM at high speed and performing arithmetic processing.

[0002]

2. Description of the Related Art Conventionally, in this type of digital data processing device, a processor processes the digital data stored in the DRAM.

FIG. 3 shows the configuration of a conventional digital data processing device. In FIG. 3, reference numeral 31 is a DRAM in which digital data is stored. 32 is a CPU
That is, the digital data is read from the DRAM 31 and data processing is performed. 33 is an address conversion circuit,
The address from the CPU 32 is received to generate a time division multiplex address of a lower address and a column address to generate the DRAM 3
Supply to 1. Reference numeral 34 is a data bus, and 35 is an address bus.

Next, the operation of this conventional configuration will be described. FIG. 4 shows processing waveforms and timings in the operation of this conventional example. In FIGS. 3 and 4, DR
It is assumed that the data to be processed by the CPU 32 is stored in advance in the AM 31. Hereinafter, the four data stored in the DRAM 31 are processed by the CPU in the order of consecutive addresses.
It is assumed that 32 reads out and performs arithmetic processing.

First, in order to read the first data, CP
The U 32 outputs the 16-bit address to the address conversion circuit 33. In the address conversion circuit 33, the CPU 3
The 16-bit address from 2 is divided into the upper 8 bits and the lower 8 bits, and then the upper 8 bits and the lower 8 bits are time-division multiplexed and supplied to the 8-bit address bus to the DRAM 31. At this time, both addresses are DRAM
While being supplied to 31, the RAS signal to the DRAM 31 is set to the low level. Also, while the lower 8 bit address is being supplied to the DRAM 31,
To the low level. As a result, D
The data stored in the designated address is output to the data bus 34 of the RAM 31. The CPU 32 takes in the data of the data bus 34 and performs data processing.

Next, the address is incremented by "1", the data is read in the same manner, and then the processing is executed. Thus, in this conventional example, the CPU 32 causes the DRA
The processing operation of the digital data stored in four consecutive addresses in M31 is completed.

[0007]

However, in the above-mentioned conventional example, as shown in FIG.
In addition, the time for reading the data of 1 word is always 2 cycles, and the time for reading the data of 4 words stored in consecutive addresses is 8 cycles in total. Therefore, there is a problem that the calculation execution speed becomes slow.

The present invention solves such a conventional problem, and is an excellent digital data processing device capable of reading data stored at consecutive addresses in a DRAM at high speed and performing arithmetic processing. The purpose is to provide.

[0009]

In order to achieve the above object, a digital data processing device of the present invention comprises a DRAM having a high speed page mode, a processor connected to the DRAM by a data bus, and a lower circuit for the DRAM. An address conversion circuit for generating two types of addresses, a time division address composed of an address and a column address, and a column address only.

[0010]

With such a configuration, the digital data processing device of the present invention operates the DRAM having the high speed page mode in the page mode so that the processor can store the data stored at the consecutive addresses in the DRAM without waiting time. Since the data is read, it is possible to read the data stored at consecutive addresses in the DRAM at high speed and perform arithmetic processing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital data processing device of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a digital data processing device of the present invention. In FIG.
Reference numeral 11 is a DRAM in which digital data is stored. A CPU 12 reads digital data from the DRAM 11 and processes this data. Reference numeral 13 is a control register, and a control value is written in accordance with an instruction from the CPU 12. 14 is an address conversion circuit,
An address from the CPU 12 is generated as a time division multiplex address of a lower address and a column address or a column address according to the control value of the control register 13, and is supplied to the DRAM 11. Reference numeral 15 is a data bus, and 16 is an address bus.

Next, the operation of the configuration of this embodiment will be described. FIG. 2 shows processing waveforms and timings in the operation in this embodiment. 1 and 2, it is assumed that data to be processed by the CPU 12 is stored in the DRAM 11 in advance. The operation in which the CPU 12 reads out the four data stored in the DRAM 11 in the order of consecutive addresses and performs the arithmetic processing will be described below.

First, before reading data from the DRAM 11, a control value "1" for notifying that the page mode operation is performed is written in the control register 13 under the control of the CPU 12. This control value is notified to the address conversion circuit 14.
After that, the CPU 12 starts reading the digital data stored in the DRAM 11. In order to read the first data, the CPU 12 outputs a 16-bit address here to the address conversion circuit 14. The address conversion circuit 14 divides the 16-bit address from the CPU 12 into upper 8 bits and lower 8 bits, and then time-division multiplexes the upper 8 bits and lower 8 bits to the 8-bit address bus to the DRAM 11 and supplies them. At this time, while both addresses are supplied to the DRAM 11, the RAS signal to the DRAM 11 is set to the low level. Further, while the lower 8-bit address is being supplied to the DRAM 11, the CAS signal to the DRAM 11 is set to the low level. In the data bus 15 of the DRAM 11,
The data corresponding to the supplied address is output. C
The PU 12 takes in the data on the data bus 15 and processes this data. Since the control value from the control register 13 is “1”, the address conversion circuit 14
After that, the page mode operation is performed.

That is, after the RAS signal to the DRAM 11 is set to the low level thereafter, the DR from the CPU 12 thereafter is set.
For the read operation to the AM 11, the lower 8 bits of the address from the CPU 12 are output to the 8-bit address bus to the DRAM 11. After that, the CAS signal is set from the high level to the low level as shown in FIG.
After the data output from 11 has stabilized, it is returned to the high level again.

The reading of data from the DRAM 11 in this page mode and the data processing are repeated three times by the CPU 12. As a result, the CPU 12 ends the processing of the four data stored in the four consecutive addresses in the DRAM 11. Thereafter, the CPU 12 writes the control value "0" in the control register 13 to notify that the page mode operation is completed and the standard operation is performed. Thus, the intended operation is completed. In the above embodiment, the column address in the page mode is four continuous addresses, but any column address on the same lower address may be specified. Further, within the refresh cycle, reading may be executed by designating any number of times. Further, in the above embodiment, the page mode is applied only when reading from the CPU 12, but the page mode can be easily expanded when writing.

In this way, the CPU 12 sets D in the control register.
When the CPU 12 sequentially generates addresses after giving a notification to operate the RAM 11 in the page mode, the control register 13 and the address conversion circuit 14 provide the page mode operation to the DRAM 11, and the processor reads the data to perform high-speed digital operation. Data processing becomes possible.

Here, assuming that the number of times of reading is N, the required number of cycles is (3 + N) cycles in this embodiment, whereas the conventional example is (2N) cycles. Therefore, if the number of times of reading N is increased, the required number of cycles can be processed in about half of the conventional example.

Further, in this circuit configuration, the control register 13
If the control value of is set to "0", the reading can be performed by the normal multiple address method instead of the page mode operation.

Further, the access speed of the CPU 12 is faster than the access speed of the DRAM 11. RISC for example
When this method is applied to the type processor, the processing can be executed with the maximum value of the processing capacity of the processor.

[0021]

As is apparent from the above description, the digital data processing device of the present invention operates the DRAM having the high speed page mode in the page mode to process the data stored at the consecutive addresses in the DRAM. Since data is read without waiting time, there is an effect that data stored in consecutive addresses in the DRAM can be read at high speed and arithmetic processing can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital data processing device of the present invention.

FIG. 2 is a timing chart showing processing waveforms and timings in the operation in the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional digital data processing device.

FIG. 4 is a timing chart showing processing waveforms and timings in the operation of the conventional example.

[Explanation of symbols]

 11 DRAM 12 CPU 13 Control Register 14 Address Conversion Circuit 15 Data Bus 16 Address Bus

Claims (1)

[Claims] 1. A DRAM having a high speed page mode,
A processor connected to the DRAM by a data bus,
An apparatus for digital data processing, comprising: an address conversion circuit for generating two kinds of addresses of a time division address consisting of a lower address and a column address and a column address only for the DRAM.