JPS639136A - Formation of bump electrode for semiconductor element - Google Patents
Formation of bump electrode for semiconductor elementInfo
- Publication number
- JPS639136A JPS639136A JP61151405A JP15140586A JPS639136A JP S639136 A JPS639136 A JP S639136A JP 61151405 A JP61151405 A JP 61151405A JP 15140586 A JP15140586 A JP 15140586A JP S639136 A JPS639136 A JP S639136A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum pad
- melting point
- aluminum
- low melting
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 44
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 43
- 230000008018 melting Effects 0.000 claims abstract description 20
- 238000002844 melting Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 14
- 239000010409 thin film Substances 0.000 abstract description 8
- 238000001259 photo etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009736 wetting Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910001316 Ag alloy Inorganic materials 0.000 description 2
- OLXNZDBHNLWCNK-UHFFFAOYSA-N [Pb].[Sn].[Ag] Chemical compound [Pb].[Sn].[Ag] OLXNZDBHNLWCNK-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［発明の技術分野］ この発明は半導体素子の突起電極形成方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for forming protruding electrodes on semiconductor devices.
［従来技術］
一般に、半導体素子を回路基板に搭載する場合には、半
導体素子のアルミパッド１ｌｉＫ（外部電極）上に金属
等からなるバンプ（突起電極）を形成し、このバンプを
回路基板の配線パターンに接続している。このようなバ
ンプの材料としては、従来、金や錫−鉛系の半田が用い
られていたが、これらの材料は半導体素子のアルミパッ
ド部上に直接形成することができないため、従来は、第
２図に示すようにして形成している。[Prior art] Generally, when mounting a semiconductor element on a circuit board, a bump (protruding electrode) made of metal or the like is formed on the aluminum pad 1liK (external electrode) of the semiconductor element, and this bump is connected to the wiring of the circuit board. connected to the pattern. Conventionally, gold or tin-lead based solder has been used as the material for such bumps, but since these materials cannot be directly formed on the aluminum pad portion of the semiconductor element, conventionally It is formed as shown in Figure 2.
即ち、第３図（Ａ）に示すように、シリコウェハ１の表
面に形成された熱酸化Ｗ２２の上面に外部電極としての
アルミパッド部３．３を形成するとともに、このアルミ
パッド部３．３を除いて酸化シリコン（ＳｉＯ２）等か
らなる絶縁性の保Ｗｉ膜４を形成する。That is, as shown in FIG. 3(A), an aluminum pad portion 3.3 as an external electrode is formed on the upper surface of the thermally oxidized W 22 formed on the surface of the silicon wafer 1, and this aluminum pad portion 3.3 is Then, an insulating Wi-retention film 4 made of silicon oxide (SiO2) or the like is formed.
この後、第３図（Ｂ）に示すように、アルミパッド部３
，３および保護膜４上に中間薄膜電極層５を基若形成す
る。この中間隙１１！２電極層５は２層の金属層からな
り、下側がクロム（Ｏｒ）層５ａで、上側が銅（Ｇｕ
）層５ｂになっている。After this, as shown in FIG. 3(B), the aluminum pad part 3
, 3 and the protective film 4, an intermediate thin film electrode layer 5 is formed thereon. This intermediate gap 11!2 electrode layer 5 consists of two metal layers, the lower side is a chromium (Or) layer 5a, and the upper side is a copper (Gu
) layer 5b.
そして、第２図（Ｃ）に示すように、中間ｇ膜電極層５
の上にメツキレシストを用いて金メッキを施し、メジキ
レシストを除去することにより金バンプ６を形成する。Then, as shown in FIG. 2(C), the intermediate G film electrode layer 5
Gold bumps 6 are formed by applying gold plating using a metallurgical resist and removing the metallurgical resist.
この後、金バンプ６をマスクして、２層の中間Ｉ８１膜
電極居５をフォトエツチング処理により、アルミパッド
部３．３以外の不要な部分を除去する。Thereafter, the gold bumps 6 are masked, and unnecessary portions other than the aluminum pad portions 3.3 are removed by photoetching the two-layer intermediate I81 film electrode layer 5.
なお、半田バンプを形成する場合には、２層の中間薄膜
電極層５をフォトエツチング処理により不要な部分を取
り除いた後、アルミパッド部３゜３上に形成された中間
薄膜電極層５上に錫−鉛系の半田を落着して、フォトエ
ツチング処理により第３図（Ｃ）と同様な半田バンプを
形成している。In addition, when forming solder bumps, after removing unnecessary portions of the two-layer intermediate thin film electrode layer 5 by photo-etching, a solder bump is formed on the intermediate thin film electrode layer 5 formed on the aluminum pad portion 3°3. Tin-lead solder is deposited and photo-etched to form solder bumps similar to those shown in FIG. 3(C).
［従来技術の問題点］
上記のようなバンプの形成方法では、アルミパッド部３
，３上にクロム（Ｃｒ）層５ａ、銅（Ｃｕ）層５ｂから
なる中間薄膜電極層５を蒸着、フォトエツチング等で形
成しなければならないので、製造工程数が多く煩雑で、
製造コストが高く、しかも２層の中間薄膜電極層５を介
して金バンプ６および半田バンプを形成しているので、
接合強度が弱い等の問題があった。[Problems with the prior art] In the above bump formation method, the aluminum pad portion 3
, 3, an intermediate thin film electrode layer 5 consisting of a chromium (Cr) layer 5a and a copper (Cu) layer 5b must be formed by vapor deposition, photoetching, etc., which requires a large number of manufacturing steps and is complicated.
The manufacturing cost is high, and the gold bumps 6 and solder bumps are formed through two intermediate thin film electrode layers 5.
There were problems such as weak bonding strength.
なお、アルミバンプを形成する場合には、アルミパッド
部３．３がアルミであるから、上述したような中間Ｓ膜
電極５を形成する必要がなく、アルミパッド部３，３上
に直接形成することができるが１回路基板との接続の際
に、超音波溶着をしなければならず、接続作業が面倒で
あり、しかも回路基板がアルミナ、ガラス等に限定され
るという問題がある。In addition, when forming an aluminum bump, since the aluminum pad portions 3.3 are made of aluminum, there is no need to form the intermediate S film electrode 5 as described above, and the intermediate S film electrode 5 can be formed directly on the aluminum pad portions 3,3. However, when connecting to a circuit board, ultrasonic welding must be performed, making the connection work troublesome, and furthermore, the circuit board is limited to materials such as alumina and glass.
［発明の目的］
この発明は上述した事情に鑑みてなされたちので、その
目的とするところは、半導体素子のアルミパッド部上に
中間薄膜電極を形成することなく、簡単かつ容易にバン
プを形成することができ、製造工程のａ素化を図るとと
もに、製造コストを下げることができる半導体素子の突
起電極形成方法を提供することにある。[Objective of the Invention] This invention has been made in view of the above-mentioned circumstances, and its purpose is to simply and easily form bumps on the aluminum pad portion of a semiconductor element without forming an intermediate thin film electrode. It is an object of the present invention to provide a method for forming protruding electrodes of a semiconductor element, which can achieve an A elemental manufacturing process and reduce manufacturing costs.
［発明の要点］
この発明は上述した目的を達成するために、半導体ウェ
ハに形成されたアルミパッド部の表面をスパッタリング
して、その表面から酸化膜を除去し、この後、前記半導
体ウェハの表面にアルミに対して濡れ性の良い低融点金
属をスパッタリング蒸着し、この蒸着された低融点金属
をアルミパッド部上だけを残して除去することにより、
アルミパッド部の表面に低融点金属のバンプを直接形成
するようにしたことを要点とする。[Summary of the Invention] In order to achieve the above-mentioned object, the present invention sputters the surface of an aluminum pad portion formed on a semiconductor wafer to remove an oxide film from the surface, and then sputters the surface of the semiconductor wafer. By sputtering a low melting point metal with good wettability to aluminum and removing the deposited low melting point metal leaving only the top of the aluminum pad,
The key point is that bumps of low melting point metal are directly formed on the surface of the aluminum pad.
［実施例］
以下、第１図を参照して、この発明の一実施例を製造工
程順に説明する。この場合、上述した従来例と同一部分
には同一符号を付し、その説明は省略する。[Example] Hereinafter, an example of the present invention will be described in order of manufacturing steps with reference to FIG. In this case, the same parts as in the conventional example described above are given the same reference numerals, and the explanation thereof will be omitted.
ま−ｒ、ｍ１図（Ａ）に示すように、シリコンウェハ１
の表面に形成された＃＃酸化膜ｚ上に外部電極としての
アルミパー２ド部３．３および酸化シリコン（Ｓｉ０２
）等からなる保：１１ａｔを形成する。そして、シリコ
ンウェハ１の表面、つまりアルミパッド部３，３および
保！Ｉ層４の表面をスパッタリング処理により、アルミ
パッド部３，３の表面から酸化膜（汚染物質）を除去す
る。これは、アルミが活性な金属であるため、空気に触
れるとただちに絶縁物である酸化膜を形成するからであ
る。m-r, m1 As shown in Figure (A), silicon wafer 1
On the ## oxide film z formed on the surface of the aluminum pad 3.3 and silicon oxide (Si02
) etc. to form a bond: 11at. Then, the surface of the silicon wafer 1, that is, the aluminum pad portions 3 and the The surface of the I layer 4 is subjected to sputtering treatment to remove the oxide film (contaminant) from the surfaces of the aluminum pad portions 3, 3. This is because aluminum is an active metal and immediately forms an oxide film, which is an insulator, when exposed to air.
この後、第１図ＣＢ）に示すように、シリコンウェハｌ
の清浄された表面に低融点金属ｌＯをスパッタリング蒸
着によりａ居形成する。この場合、低融点金１ｉ１Ｅ１
０はアルミに対して濡れ性の良いもので１例えば、錫−
至鉛系合金や、錫−鉛一銀系合金等である。錫−亜鉛系
合金としては、日本アルミツト社製のＡ）ｌ−０２２（
融点２２０℃）や、千住金属工業社製のＡＬ−２００（
融点２７０℃）等があり、錫−鉛一銀系合金としては、
ロ木スペリア社製のＡＬ［＋−３ＯＬ４５Ｄ（融点２０
０℃）等がある。After this, as shown in FIG. 1 CB), the silicon wafer l
A low melting point metal 1O is formed on the cleaned surface by sputtering deposition. In this case, low melting point gold 1i1E1
0 indicates good wettability to aluminum; 1, for example, tin-
These include lead-based alloys, tin-lead-silver alloys, etc. As a tin-zinc alloy, A) l-022 (manufactured by Nippon Aluminum Co., Ltd.) is used.
melting point 220℃), AL-200 manufactured by Senju Metal Industry Co., Ltd.
melting point 270℃), etc., and as a tin-lead-silver alloy,
AL[+-3OL45D (melting point 20
0℃) etc.
このような低融点金属１０をフォトエツチング処理によ
り、アルミパッド部３，３上だけを残して、不要な部分
を除去し、この後、リフロー（熱を加える処理）すると
、第１図（Ｃ）に示すように、アルミパッド部３．３上
にアルミ用半田バンプ１１．１１が形成される。なおこ
の半田パンプ１１．１１が形成されたシリコンウェハｌ
は各半導体チップｌ ａｅ 轡・毎に同図に１点鎖線で
示すような位置でダイシングにより切断される。When such a low melting point metal 10 is photoetched to remove unnecessary parts, leaving only the tops of the aluminum pads 3, 3, and then reflowed (processing to apply heat), the result is shown in FIG. 1(C). As shown in FIG. 3, solder bumps 11.11 for aluminum are formed on the aluminum pad portion 3.3. Note that the silicon wafer l on which this solder pump 11.11 is formed is
Each semiconductor chip is cut by dicing at the position shown by the dashed line in the figure.
このようにして得られた半導体チップｌａを回路基板１
２に接続する場合には、第２図に示すように、半導体チ
ップ１ａの半田バンプ１１．１１と１回路基板１２に形
成された配線リード１３．１３とを位置合わせし、この
状態で、両者をパルスヒート方式等で接続することによ
り、半田パンプ１１．１１を介して半導体チップ１ａの
アルミパッド部３．３と回路基板１２の配線リード１３
．１３とが電気的に接続される。この場合、回路基板１
２はフィルム等からなるフレキシブルなものであり、そ
の下面に形成される配線リード１３．１３は銅、あるい
は銅に金、半田（錫−鉛系）、錫等をメッキしたものが
用いられ、接着剤５１４を介して回路基板１２に接着さ
れている。The semiconductor chip la thus obtained is placed on a circuit board 1.
2, as shown in FIG. By connecting them using a pulse heating method or the like, the aluminum pad portion 3.3 of the semiconductor chip 1a and the wiring lead 13 of the circuit board 12 are connected via the solder pump 11.11.
．． 13 are electrically connected. In this case, circuit board 1
2 is a flexible material made of film or the like, and the wiring leads 13.13 formed on the bottom surface are made of copper or copper plated with gold, solder (tin-lead type), tin, etc., and are bonded. It is adhered to the circuit board 12 via an adhesive 514.
［発明の効果］
以上詳細に説明したように、この発明は、半導体ウェハ
の表面にアルミに対して濡れ性の良い低融点金属をスパ
ッタリング蒸着し、この蒸着された低融点金属をアルミ
パッド部上だけを残して除去することにより、アルミパ
ッド部の表面に低融点金属のバンプを直接形成するよう
にしたので、従来のような中間薄膜電極を形成すること
なく、簡単かつ容易にバンプを形成することができ、製
造工程の簡素化を図ることができるとともに、製造コス
トを下げることができる等の効果がある。[Effects of the Invention] As explained above in detail, the present invention involves sputtering vapor deposition of a low melting point metal that has good wettability to aluminum on the surface of a semiconductor wafer, and applying the vapor deposited low melting point metal onto an aluminum pad portion. By removing only the aluminum pad, a low melting point metal bump is formed directly on the surface of the aluminum pad, making it easy to form bumps without having to form an intermediate thin film electrode like in the past. This has the effect of simplifying the manufacturing process and reducing manufacturing costs.
第１図（Ａ）〜（Ｃ）はこの発明の形成工程を示す図、
第２図は半導体チップと回路基板との接続状態を示す図
、第３図（Ａ）〜（Ｃ）は従来の形成工程を示す図であ
る。
１・・・・・・シリコンウェハ、ｌａ・・・・・・半導
体チップ、３，３・・・・・・アルミパー２ト部、４・
・・・・・保ｙｓ膜、ｌＯ・・・・・・低融点金属、１
１・・・用アルミ用半田バンプ。
特許出願人 カシオ計算機株式会社
ハ”Ｉフ’／＋４９Ｋｃｎ＋Ｊ−ＫｒＨΔ第２図
りＣ）位しめ掲比に弊（ホ４めFIGS. 1(A) to 1(C) are diagrams showing the forming process of this invention,
FIG. 2 is a diagram showing a connection state between a semiconductor chip and a circuit board, and FIGS. 3(A) to 3(C) are diagrams showing a conventional forming process. 1... Silicon wafer, la... Semiconductor chip, 3, 3... Aluminum part 2 part, 4...
... ys retention film, lO ... low melting point metal, 1
1 Solder bump for aluminum. Patent applicant: Casio Computer Co., Ltd.
Claims (1)
被覆された半導体ウェハの表面をスパッタリングし、各
アルミパッド部の酸化膜を除去する工程と、 前記半導体ウェハの表面にアルミに対して濡れ性の良い
低融点金属をスパッタリング蒸着する工程と、 蒸着された低融点金属をアルミパッド部上だけを残して
除去する工程と、 を備えたことを特徴とする半導体素子の突起電極形成方
法。[Scope of Claims] A step of sputtering the surface of a semiconductor wafer covered with a protective film leaving only the aluminum pad portion of each semiconductor element to remove an oxide film on each aluminum pad portion, and the surface of the semiconductor wafer. A semiconductor device comprising: a step of sputtering a low melting point metal with good wettability to aluminum to deposit it; and a step of removing the deposited low melting point metal leaving only on the aluminum pad portion. Method for forming protruding electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61151405A JPH0815153B2 (en) | 1986-06-30 | 1986-06-30 | Method for forming protruding electrode of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61151405A JPH0815153B2 (en) | 1986-06-30 | 1986-06-30 | Method for forming protruding electrode of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS639136A true JPS639136A (en) | 1988-01-14 |
| JPH0815153B2 JPH0815153B2 (en) | 1996-02-14 |
Family
ID=15517870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61151405A Expired - Lifetime JPH0815153B2 (en) | 1986-06-30 | 1986-06-30 | Method for forming protruding electrode of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0815153B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0494463A2 (en) * | 1991-01-09 | 1992-07-15 | Kabushiki Kaisha Toshiba | Connection method and connection device for electrical connection of small portions |
-
1986
- 1986-06-30 JP JP61151405A patent/JPH0815153B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0494463A2 (en) * | 1991-01-09 | 1992-07-15 | Kabushiki Kaisha Toshiba | Connection method and connection device for electrical connection of small portions |
| EP0494463B1 (en) * | 1991-01-09 | 1999-03-31 | Kabushiki Kaisha Toshiba | Connection method and connection device for electrical connection of small portions |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0815153B2 (en) | 1996-02-14 |
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