JP2768448B2 - Method of forming solder bumps - Google Patents
Method of forming solder bumpsInfo
- Publication number
- JP2768448B2 JP2768448B2 JP1340131A JP34013189A JP2768448B2 JP 2768448 B2 JP2768448 B2 JP 2768448B2 JP 1340131 A JP1340131 A JP 1340131A JP 34013189 A JP34013189 A JP 34013189A JP 2768448 B2 JP2768448 B2 JP 2768448B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- solder bump
- solder
- forming
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半田バンプの形成方法に関する。The present invention relates to a method for forming a solder bump.
さらに詳しくは、半導体ウエハ、半導体チップ等の半
導体素子類やセラミック回路基板、ガラス回路基板、プ
リント配線基板等の基板類に形成されているCu配線上ま
たはNi配線上に半田バンプを形成する方法の改良に関す
る。More specifically, a method of forming solder bumps on Cu wiring or Ni wiring formed on substrates such as semiconductor elements such as semiconductor wafers, semiconductor chips, and ceramic circuit boards, glass circuit boards, and printed wiring boards. Regarding improvement.
［従来の技術］ 従来、半田バンプの形成手段として、本出願人は特願
昭63−301535号を先に提案している。[Prior Art] Conventionally, as a means for forming solder bumps, the present applicant has previously proposed Japanese Patent Application No. 63-301535.
この本出願人の先提案では、バンプ材料として特に有
用な半田材料として開発したPb−Sn系合金をワイヤ状に
形成してなる半田ワイヤを用いて、半田ワイヤの先端を
加熱球状化して配線に当触切断するワイヤボンダ法によ
り半田バンプを形成するものである。In the prior proposal of the present applicant, a solder wire formed by forming a Pb-Sn-based alloy into a wire shape developed as a solder material particularly useful as a bump material is used. The solder bumps are formed by a wire bonder method for performing contact cutting.
［発明が解決しようとする課題］ 前述の本出願人の先提案では、Cu配設上またはNi配線
上に半田バンプを形成する場合、加熱球状化された半田
ワイヤの先端のブリネリ硬さ（HB＝10）に対してCu配
線,Ni配線が硬すぎることから、半田バンプとCu配線,Ni
配線との有効な接合強度を得ることができないという問
題点を有している。[Problems to be Solved by the Invention] According to the above-mentioned prior proposal of the present applicant, when forming solder bumps on Cu disposition or Ni wiring, the Brineri hardness (HB = 10) Cu and Ni wiring are too hard for solder bumps and Cu wiring, Ni
There is a problem that an effective bonding strength with the wiring cannot be obtained.
本発明は、このような問題点を考慮してなされたもの
で、半田バンプとCu配線,Ni配線とを強固に接合するこ
とのできる半田バンプの形成方法を提供することを課題
とする。The present invention has been made in consideration of such problems, and has as its object to provide a method for forming a solder bump capable of firmly joining a solder bump to a Cu wiring or a Ni wiring.
［課題を解決するための手段］ 前述の課題を解決するため、本発明に係る半田バンプ
の形成方法は、次のような手段を採用する。[Means for Solving the Problems] In order to solve the above-mentioned problems, a method for forming a solder bump according to the present invention employs the following means.
即ち、請求項１では、Pb,In,Snを主要元素とする半田
ワイヤを用いてワイヤボンダ法によりCu配線上またはNi
配線上に半田バンプを形成する半田バンプの形成方法に
おいて、Cu配線上またはNi配線上のバンプ形成予定部分
に予めAu,Ag,Pt,Pd,Pb,Sn,In,Pb−Sn,Pb−Inからなる薄
膜を被覆しておくことを特徴とする。In other words, in the first aspect, a solder wire containing Pb, In, and Sn as main elements is used to form a Cu wire or a Ni wire by a wire bonding method.
In a method of forming a solder bump on a wiring, a method of forming a solder bump on a Cu wiring or a Ni wiring in advance by forming a Au, Ag, Pt, Pd, Pb, Sn, In, Pb-Sn, Pb-In Characterized by being coated with a thin film consisting of
また、請求項２では、請求項１の半田バンプの形成方
法において、薄膜の膜厚を0.001μｍ以上とすることを
特徴とする。According to a second aspect, in the method for forming a solder bump of the first aspect, the thickness of the thin film is set to 0.001 μm or more.
［作用］ 前述の手段によると、半田バンプとCu配線,Ni配線と
の間に介在することになる薄膜（特に、膜厚を0.001μ
ｍ以上とすると）が半田バンプとCu配線,Ni配線との接
合強度を補強するため、半田バンプとCu配線,Ni配線と
を強固に接合することのできる半田バンプの形成方法を
提供するという課題が解決される。[Operation] According to the above-mentioned means, a thin film (particularly, a film thickness of 0.001 μm) to be interposed between the solder bump and the Cu wiring or the Ni wiring.
The problem is to provide a method for forming a solder bump that can firmly join the solder bump to the Cu wiring and the Ni wiring in order to reinforce the bonding strength between the solder bump and the Cu wiring and the Ni wiring. Is resolved.
［実施例］ 以下、本発明に係る半田バンプの形成方法の実施例を
図面に基いて説明する。Example An example of a method for forming a solder bump according to the present invention will be described below with reference to the drawings.
第１図は、本発明に係る半田バンプの形成方法の第１
実施例を示すものである。FIG. 1 shows a first method of forming a solder bump according to the present invention.
It shows an embodiment.
この実施例では、プリント配線基板１に無電解メッキ
手段により形成されたCu配線２上に半田バンプ３を形成
するものを示してある。In this embodiment, a solder bump 3 is formed on a Cu wiring 2 formed on a printed wiring board 1 by electroless plating.
この実施例のCu配線２は、半導体チップ４の実装のた
めの部分を残してポリイミド等の絶縁材からなる保護膜
５が被覆されている。The Cu wiring 2 of this embodiment is covered with a protective film 5 made of an insulating material such as polyimide, except for a portion for mounting the semiconductor chip 4.
このようなCu配線２に対して、まず、第１図Ａに示す
ように半田バンプ形成予定部分（半導体チップ４の実装
のための部分）に無電解Snメッキ手段により薄膜６を被
覆する。First, as shown in FIG. 1A, a thin film 6 is coated on a portion where a solder bump is to be formed (a portion for mounting the semiconductor chip 4) on the Cu wiring 2 by electroless Sn plating.
続いて、第１図Ｂに示すように、前述した本出願人の
先提案に係るワイヤボンダ法によって、薄膜６上に半田
バンプ３を形成する。この半田バンプ３を形成する半田
材料、必ずしも本出願人の先提案に係るPb−Sn系合金に
限られず、Pb,In,Snを主要元素とする一般的なもので差
支えない。Subsequently, as shown in FIG. 1B, the solder bumps 3 are formed on the thin film 6 by the wire bonding method according to the above-mentioned prior proposal of the present applicant. The solder material for forming the solder bump 3 is not necessarily limited to the Pb-Sn-based alloy according to the earlier proposal of the present applicant, and may be a general material containing Pb, In, and Sn as main elements.
而後、第１図（Ｃ）に示すようにリフロー炉等によっ
て半田バンプ３の半田ワイヤからの切断端を球状化処理
し、第１図（Ｄ）に示すように半導体チップ４を実装す
るのである。Thereafter, as shown in FIG. 1 (C), the cut end of the solder bump 3 from the solder wire is subjected to spheroidizing treatment by a reflow furnace or the like, and the semiconductor chip 4 is mounted as shown in FIG. 1 (D). .
このような実施例によると、薄膜６の被覆工作は簡単
に行なうことができ、被覆によって半田バンプ３とCu配
線２との間に介在することになる薄膜６が、半田バンプ
３とCu配線２との間で硬度的なクッション機能を奏する
とともに両者の接合強度を補強することになる。本発明
による実験では、薄膜６の膜厚を0.001μｍ以上とする
と、極めて良好な半田バンプ３とCu配線２との接合強度
を得ることができた。According to such an embodiment, the coating work of the thin film 6 can be easily performed, and the thin film 6 to be interposed between the solder bump 3 and the Cu wiring 2 by the coating is formed by the solder bump 3 and the Cu wiring 2. And a hard cushion function between them, and the joint strength between them is reinforced. In the experiment according to the present invention, when the thickness of the thin film 6 was 0.001 μm or more, it was possible to obtain an extremely good bonding strength between the solder bump 3 and the Cu wiring 2.
第２図は、本発明に係る半田バンプの形成方法の第２
実施例を示すものである。FIG. 2 is a cross-sectional view of a method for forming a solder bump according to the present invention.
It shows an embodiment.
この実施例では、半導体チップに無電解メッキ手段に
より形成されたNi配線７上に半田バンプ３を形成するも
のを示してある。In this embodiment, a solder bump 3 is formed on a Ni wiring 7 formed on a semiconductor chip by electroless plating means.
この実施例のNi配線７は、配線基板８への実装のため
の部分を残してポリイミド等の絶縁材からなる保護膜９
が被覆されている。The Ni wiring 7 of this embodiment has a protective film 9 made of an insulating material such as polyimide except for a part for mounting on a wiring board 8.
Is coated.
このようなNi配線７に対して、まず、第２図（Ａ）に
示すように半田バンプ形成予定部分（配線基板８への実
装のための部分）に無電解Auメッキ手段により薄膜６を
被覆する。First, as shown in FIG. 2 (A), a thin film 6 is coated on a portion where solder bumps are to be formed (a portion for mounting on a wiring board 8) by electroless Au plating. I do.
続いて、第２図Ｂに示すように、前述した本出願人の
先提案に係るワイヤボンダ法によって、薄膜６上に半田
バンプ３を形成する。この半田バンプ３を形成する半田
材料は、必ずしも本出願人の先提案に係るPb−Sn系合金
に限られず、Pb,In,Snを主要元素とする一般的なもので
差支えない。Subsequently, as shown in FIG. 2B, the solder bumps 3 are formed on the thin film 6 by the wire bonding method according to the above-mentioned prior proposal of the present applicant. The solder material forming the solder bumps 3 is not necessarily limited to the Pb-Sn based alloy according to the prior proposal of the present applicant, but may be a general material containing Pb, In, and Sn as main elements.
而後、第２図（Ｃ）に示すようにリフロー炉等によっ
て半田バンプ３の半田ワイヤからの切断端を球状化処理
し、第２図（Ｄ）に示すように配線基板８へ実装するの
である。Thereafter, the cut end of the solder bump 3 from the solder wire is subjected to spheroidizing treatment by a reflow furnace or the like as shown in FIG. 2 (C), and is mounted on the wiring board 8 as shown in FIG. 2 (D). .
このような実施例によると、第１実施例と同様の作
用、効果を得ることができ、薄膜６の膜厚についても同
様の結果が得られた。According to such an embodiment, the same operation and effect as those of the first embodiment can be obtained, and similar results can be obtained for the thickness of the thin film 6.
以上、図示した実施例の外に、膜厚６の被覆を電気メ
ッキ手段、蒸着手段、スパッタリング手段で行なう実施
例も可能である。As described above, in addition to the illustrated embodiment, an embodiment in which coating with a film thickness of 6 is performed by an electroplating unit, a vapor deposition unit, or a sputtering unit is also possible.
さらに、薄膜６の材質をAg,Pt,Pd,Pb,In,Pb−Sn,Pb−
Inとする実施例も可能である。Further, the material of the thin film 6 is made of Ag, Pt, Pd, Pb, In, Pb-Sn, Pb-
An embodiment in which In is set is also possible.
さらに、半田バンプ３の半田ワイヤからの切断端の球
状化処理を行なわずに実装を行う実施例とすることも可
能である。Further, an embodiment may be adopted in which the mounting is performed without performing the spheroidizing process of the cut end of the solder bump 3 from the solder wire.
［発明の効果］ 以上のように本発明に係る半田バンプの形成方法は、
請求項１では、半田バンプとCu配線、Ni配線との間に介
在することになる薄膜が半田バンプとCu配線,Ni配線と
の接合強度を補強するため、半田バンプとCu配線,Ni配
線とが強固に接合される効果がある。[Effects of the Invention] As described above, the method for forming a solder bump according to the present invention includes:
According to claim 1, the thin film interposed between the solder bump and the Cu wiring or the Ni wiring reinforces the bonding strength between the solder bump and the Cu wiring or the Ni wiring. Has the effect of being strongly bonded.
さらに、薄膜の被覆工作を簡単に行なうことができる
ため、実装コスト、実装手間が掛らない効果がある。Further, since the coating operation of the thin film can be easily performed, there is an effect that mounting cost and mounting time are not required.
また、請求項２では、請求項１の効果に加えて、半田
バンプCu配線,Ni配線との接合強度がさらに向上する効
果がある。According to the second aspect, in addition to the effect of the first aspect, there is an effect that the bonding strength with the solder bump Cu wiring and the Ni wiring is further improved.
第１図は本発明に係る半田バンプの形成方法の第１実施
例を示すもので（Ａ）〜（Ｄ）の順に工程を示すもので
あり、第２図は同第２実施例を示すもので（Ａ）〜
（Ｄ）の順に工程を示すものである。 ２……Cu配線、３……半田バンプ ６……薄膜、７……Ni配線FIG. 1 shows a first embodiment of a method for forming a solder bump according to the present invention, showing the steps in the order of (A) to (D), and FIG. 2 shows the second embodiment. And (A) ~
The steps are shown in order of (D). 2 ... Cu wiring, 3 ... Solder bump 6 ... Thin film, 7 ... Ni wiring
Claims (2)
いてワイヤボンダ法によりCu配線上またはNi配線上に半
田バンプを形成する半田バンプの形成方法において、Cu
配線上またはNi配線上のバンプ形成予定部分に予めAu,A
g,Pt.Pd,Pb,Sn,In,Pb−Sn,Pb−Inからなる薄膜を被覆し
ておくことを特徴とする半田バンプの形成方法。A method for forming a solder bump on a Cu wiring or a Ni wiring by a wire bonder method using a solder wire containing Pb, In, Sn as a main element.
Au, A
g, Pt. Pd, Pb, Sn, In, Pb-Sn, and Pb-In.
て、薄膜の膜厚を0.001μｍ以上とすることを特徴とす
る半田バンプの形成方法。2. The method for forming a solder bump according to claim 1, wherein the thickness of the thin film is 0.001 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1340131A JP2768448B2 (en) | 1989-12-27 | 1989-12-27 | Method of forming solder bumps |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1340131A JP2768448B2 (en) | 1989-12-27 | 1989-12-27 | Method of forming solder bumps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03200343A JPH03200343A (en) | 1991-09-02 |
| JP2768448B2 true JP2768448B2 (en) | 1998-06-25 |
Family
ID=18334023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1340131A Expired - Lifetime JP2768448B2 (en) | 1989-12-27 | 1989-12-27 | Method of forming solder bumps |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2768448B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2783093B2 (en) * | 1992-10-21 | 1998-08-06 | 日本電気株式会社 | Printed wiring board |
| JPH09102517A (en) * | 1995-10-05 | 1997-04-15 | Nec Corp | Semiconductor device |
| KR100233996B1 (en) * | 1996-12-11 | 1999-12-15 | 전주범 | Light path apparatus with advanced via contact |
| EP1915040A3 (en) | 2001-09-28 | 2008-04-30 | Ibiden Co., Ltd. | Printed wiring board and printed wiring board manufacturing method |
-
1989
- 1989-12-27 JP JP1340131A patent/JP2768448B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03200343A (en) | 1991-09-02 |
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