JPS6390834U - - Google Patents

Info

Publication number
JPS6390834U
JPS6390834U JP18628286U JP18628286U JPS6390834U JP S6390834 U JPS6390834 U JP S6390834U JP 18628286 U JP18628286 U JP 18628286U JP 18628286 U JP18628286 U JP 18628286U JP S6390834 U JPS6390834 U JP S6390834U
Authority
JP
Japan
Prior art keywords
semiconductor element
mounting plate
silicon
medium
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18628286U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18628286U priority Critical patent/JPS6390834U/ja
Publication of JPS6390834U publication Critical patent/JPS6390834U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
図面は、この考案の半導体装置の一実施例の断
面図である。 1…半導体素子、2…鉄製の取り付け板、3…
半田層。

Claims (1)

    【実用新案登録請求の範囲】
  1. 材料がシリコンの半導体素子と、この半導体素
    子を取り付ける鉄製の取り付け板とにより構成さ
    れた中容量のパワー半導体装置。
JP18628286U 1986-12-03 1986-12-03 Pending JPS6390834U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18628286U JPS6390834U (ja) 1986-12-03 1986-12-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18628286U JPS6390834U (ja) 1986-12-03 1986-12-03

Publications (1)

Publication Number Publication Date
JPS6390834U true JPS6390834U (ja) 1988-06-13

Family

ID=31135700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18628286U Pending JPS6390834U (ja) 1986-12-03 1986-12-03

Country Status (1)

Country Link
JP (1) JPS6390834U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5079265A (ja) * 1973-11-09 1975-06-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5079265A (ja) * 1973-11-09 1975-06-27

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