JPS6390372U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1A is a block circuit diagram showing an embodiment of the present invention, FIG. 1B is a waveform diagram showing the timing of a synchronizing signal, and FIG. 2 is a block circuit diagram showing a conventional example. Explanation of symbols of main parts, 6...Oscillation circuit, 20,
22...Switch, 21...Frequency dividing circuit.

Claims (1)

[Scope of utility model registration request] While displaying a composite video signal including horizontal and vertical synchronizing signals as a two-dimensional image, the pattern information signal is displayed at one point in one horizontal scanning section on a display means that preferentially displays the pattern information signal that is supplied by interruption. The pattern information generating device supplies the pattern information at a timing corresponding to the composite video signal, and includes variable frequency dividing means for frequency dividing the horizontal synchronizing signal separated from the composite video signal at a variable frequency division ratio, and a clock pulse at a variable period. a variable clock generating means for generating a clock, a timing setting means for determining the timing based on the divided horizontal synchronizing signal and the clock pulse, and a timing setting means for setting the frequency division ratio of the variable frequency dividing circuit and the clock frequency of the variable clock generating means to each other. A pattern information generating device characterized by comprising an adjusting means for changing it in inverse proportion.