JPH02126191U - - Google Patents
Info
- Publication number
- JPH02126191U JPH02126191U JP3498689U JP3498689U JPH02126191U JP H02126191 U JPH02126191 U JP H02126191U JP 3498689 U JP3498689 U JP 3498689U JP 3498689 U JP3498689 U JP 3498689U JP H02126191 U JPH02126191 U JP H02126191U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- polarity inversion
- circuit
- frequency
- shift clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Transforming Electric Information Into Light Information (AREA)
Description
第１図は、本考案の一実施例の回路図を示した
ものである。第２図は、第１図のタイミング図を
示したものである。第３図は、従来の回路図を示
したものである。第４図は、第３図のタイミング
図を示したものである。
１，４……1/4分周回路、２……同期化回路、
３，５……排他的論理和回路、ＣＬ１……シフト
クロツク信号、ＦＬＭ……フレーム信号、Ｍ……
第１の極性反転信号、ＤＦＭ……第２の極性反転
信号。
FIG. 1 shows a circuit diagram of an embodiment of the present invention. FIG. 2 shows the timing diagram of FIG. 1. FIG. 3 shows a conventional circuit diagram. FIG. 4 shows the timing diagram of FIG. 3. 1, 4...1/4 frequency divider circuit, 2...synchronization circuit,
3, 5...Exclusive OR circuit, CL1...Shift clock signal, FLM...Frame signal, M...
First polarity inversion signal, DFM...second polarity inversion signal.
Claims (1)
トクロツク信号が入力され、シフトクロツク信号
を分周する分周回路と、この分周回路の分周信号
及びフレーム毎に極性反転する第１の極性反転信
号を前記シフトクロツクと同期化する同期化手段
と、同期化された分周信号及び第１の極性反転信
号を排他的論理和する排他的論理和回路とを有し
、 この排他的論理和回路からの出力を極性反転駆
動信号としたことを特徴とする液晶表示装置の極
性反転信号発生回路。 ２ 分周回路は、シフトクロツク信号を1/4分周
する分周回路より構成されたことを特徴とする請
求項１記載の液晶表示装置の極性反転信号発生回
路。[Claims for Utility Model Registration] 1. A frequency dividing circuit which receives a frame signal and a shift clock signal for line-sequential scanning and divides the frequency of the shift clock signal, and the divided signal of this frequency dividing circuit and the polarity inversion for each frame. a synchronizing means for synchronizing a first polarity inversion signal to be output with the shift clock; and an exclusive OR circuit for exclusive ORing the synchronized frequency division signal and the first polarity inversion signal; A polarity inversion signal generation circuit for a liquid crystal display device, characterized in that an output from an exclusive OR circuit is used as a polarity inversion drive signal. 2. The polarity inversion signal generating circuit for a liquid crystal display device according to claim 1, wherein the frequency dividing circuit is constituted by a frequency dividing circuit that divides the frequency of the shift clock signal by 1/4.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989034986U JP2540686Y2 (en) | 1989-03-28 | 1989-03-28 | Liquid crystal display |
| EP19890308084 EP0355054A3 (en) | 1988-08-19 | 1989-08-09 | Control circuit for a matrix display |
| KR1019890011688A KR900003671A (en) | 1988-08-19 | 1989-08-17 | Alternating current drive control circuit of matrix display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989034986U JP2540686Y2 (en) | 1989-03-28 | 1989-03-28 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02126191U true JPH02126191U (en) | 1990-10-17 |
| JP2540686Y2 JP2540686Y2 (en) | 1997-07-09 |
Family
ID=31539949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989034986U Expired - Lifetime JP2540686Y2 (en) | 1988-08-19 | 1989-03-28 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2540686Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61100731A (en) * | 1984-10-23 | 1986-05-19 | Seiko Instr & Electronics Ltd | Liquid crystal display device |
| JPS63274932A (en) * | 1987-05-06 | 1988-11-11 | Seiko Instr & Electronics Ltd | Liquid crystal driving circuit |
-
1989
- 1989-03-28 JP JP1989034986U patent/JP2540686Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61100731A (en) * | 1984-10-23 | 1986-05-19 | Seiko Instr & Electronics Ltd | Liquid crystal display device |
| JPS63274932A (en) * | 1987-05-06 | 1988-11-11 | Seiko Instr & Electronics Ltd | Liquid crystal driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2540686Y2 (en) | 1997-07-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |