JPH0195824U

JPH0195824U -

Info

Publication number: JPH0195824U
Application number: JP19128887U
Authority: JP
Priority date: 1987-12-18
Filing date: 1987-12-18
Publication date: 1989-06-26

Description

[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク構成図、
第２図はそのクロツク発生回路の動作説明図、第
３図はパルス同期化回路の動作説明図、第４図は
従来例のブロツク構成図である。図面中、１は発振器、３はカウンタ、２０と３
０は同期化されるべきパルス信号、２２，２４，
３２及び３４はＤフリツプフロツプ、２６，３６
，４１及び４７は論理積素子、２８と３８は同期
化された出力パルス、４０はクロツク発生回路、
４３と４９は遅延素子、４５は否定論理素子であ
る。 FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the operation of the clock generation circuit, FIG. 3 is an explanatory diagram of the operation of the pulse synchronization circuit, and FIG. 4 is a block diagram of the conventional example. In the drawing, 1 is an oscillator, 3 is a counter, 20 and 3
0 is the pulse signal to be synchronized, 22, 24,
32 and 34 are D flip-flops, 26, 36
, 41 and 47 are AND elements, 28 and 38 are synchronized output pulses, 40 is a clock generation circuit,
43 and 49 are delay elements, and 45 is a negative logic element.

Claims

[Claims for Utility Model Registration] In a circuit that synchronizes two asynchronously input pulse signals using four clock signals, a clock signal input from an oscillator and a signal obtained by dividing this clock signal into 1/2 are used. comprising an AND element that takes the logical product of and a delay element that delays the output signal of the AND element, and includes a circuit that outputs the output signal of the AND element and the output signal of the delay element as a pair of clock signals, Furthermore, the clock signal from the oscillator is halved.
a NOT logic element that inverts a signal whose frequency has been divided into 1, an AND element that ANDs the output signal of the NOT logic element and the clock signal from the oscillator, and a delay element that delays the output signal of the AND element. Then, the output signal of the AND element and the output signal of the delay element are set to 1.
A pulse synchronization circuit characterized by comprising a circuit that outputs a pair of clock signals.