JPS61100731A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent a liquid crystal display device from the uneveness of display due to cross talk by setting up the polarity inverting frequency of a voltage to be impressed to liquid crystal to 6-7 times the frame frequency at the selection of a non-electrode, changing the polarity in each frame and executing AC driving. CONSTITUTION:At the input of a polarity inverting signal, the phase of a signal outputted from a frequency dividing circuit 22 is inverted and the phase-inverted signal is inputted to the control terminals of two pairs of analog switches 20a, 20b and 20c, 20d in a driving voltage generating circuit 20 directly or through an inverter 24 to output zero potential and 2/aVop or Vop and (1-2/a)Vop from the circuit 20. Voltage from the circuit 20 is applied to an output gate 21 consisting of a pair of analog switches 21a, 21b, an output signal from a latch circuit 19 is directly inputted to one analog switch 21a and the output signal is inverted by an inverter 25 and then inputted to the other analog switch 21b. In this case, the polarity inverting frequency of the voltage to be impressed to the liquid crystal at the selection of the non-electrode is 6-7 times the frame frequency.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a display device using liquid crystal.

[Prior art]

In recent years, the dot matrix. As a type of display device, liquid crystal display devices are attracting attention, and progress is being made in the direction of larger screens and an increase in the number of scanning lines.

Conventionally, the dynamic driving method of a liquid crystal display device is a method of completely reversing the polarity of the voltage applied to the liquid crystal when four electrodes are selected and when no electrode is selected every scanning time of all scanning lines tl-1 times (hereinafter referred to as "current driving"). This is called a two-frame father-flow drive system.

For example, Nikkei Electronics 1980.8°18,
Shown in P2S5-P174.

Next, the drive circuit will be explained.

FIG. 7 shows a conventional example of a common electrode drive circuit, and the reference numeral 27 in the figure is a shift register, and the line-sequential depletion signal KECOMON'KAME@! , Kuro72 synchronized with running speed
No. 45 is sequentially shifted. 28U, the launch circuit launches No. 2 from the shift register 27 in synchronization with the clock signal, and activates the activation button production Ljl, which will be described later.
The driving voltage from the line 60 is passed through the blade gate circuit 52 to the common electrode CtH.

C4,...Q M'n. Reference numeral 60 denotes the aforementioned drive voltage generation circuit, which connects analog switches 31a and 51'b, such as switches from a power source (not shown), to
.

51c, 51d, the liquid crystal driven pressure Vop
and an analog switch 61 supplied with zero pressure.
a and 51 b'ii, also (1--)Vop, -v
The outputs of analog switches 51Q and 51 (1) supplied with opa a are output as a pair to an output gate 29, which will be described later.

are doing. Here, when a is the number of set meal lines fD, it is expressed as 1 section, /n-)1.

The polarity inversion signal is input directly and via the inverter 55 to the control terminals of the seven analog switches 51a, 51'b, and 31c31d of the drive IIIJ voltage generation circuit 60, and is output from the drive voltage generation circuit 50 to zero potential and ( 1--) Vo
p or VOp and -VOp total output a
It's grown to 1 so that I can sleep with you. Reference numeral 29 denotes a pair of analog switches 52a and 52bi, each of which receives all voltage supply from the drive voltage generation circuit 60, and one of the analog switches 52a receives the output signal from the launch circuit 28T directly to V. The other analog switch 52b receives an inverted signal from the inverter 16.

Fig. 8 shows a typical example of the segment 1 JL polar tortuosity circuit. In the figure, reference numeral 5B is a shift ratio, and the data signal and the segment ball polar movement timing, that is, the secondary running hill long cx2 are input. and clock the data signal CK
It is configured to shift by 2. Reference numeral 39 denotes a launch circuit, which launches in synchronization with the clock signal CK2 from the shift register 58, and receives the driving voltage from the drive voltage generation circuit 56, which will be described later.
Through segment '&, Sorry''G1 + 'G2
+ ・・・This is what is supplied to sG&. Reference numeral 56 denotes analog switches 56a and 56b such as gates in the drive voltage generating circuit described above.

56c and 56df, and the liquid crystal drive voltage Vop
and an analog switch 56a supplied with zero potential.
and 56bf:, also (1--)Vop, -Vop a
a The outputs of the analog switches 56c and 56d that receive the supply are output as a pair to an output gate 67, which will be described later.

The polarity inversion signal is applied directly or via the inverter 34 to the analog switch 36a of the drive voltage generation circuit 56.
, 56b, 56c, and 36d, and the $ potential and ヱVop or Vop are input from the drive voltage generation circuit 66.
and (1-s) Output Vop a
a. Reference numeral 57 designates an output gate consisting of a pair of two analog switches 57a and 57bf, which respectively supply voltage from the drive 'I' and pressure generation circuit 56'jk.
one analog switch 67a is the launch circuit 59
The output signal from the other analog switch 7
The signal is inverted by an inverter 65 and input to b.

Next, the complete set of operations of the device configured in this way is shown in Figure 7.
'I will explain the mackerel based on the C and shape diagram.

When the line 1 section next run signal is output, it is launched by the launch circuit 28 via the shift register 27, and the first common electrode cME becomes the selected state, and the other common electrodes CM≦...CM' n becomes unselected.

On the other hand, when the inertia reversal signal is at low level, the drive I
j7JX pressure generation 1 smell 1 road 50 Vop, -Vop
is output, Vo'p is output to the common electrode CMζ, and -Vop is output to the other common electrodes.

Segment)'FRi, in the pole drive circuit (Fig. 8), when the polarity inversion signal is at Low level, zero potential, -Vop, is output from the drive' heavy pressure generation circuit. Launch circuit 5
When the data output from TJ is high, the segment is in the selected state and outputs zero potential.
When in OW, -Vop becomes unusable.

FIG. 9 shows the case where all the data signals are in the lit state, and the output shaping varies depending on the case of cM(.

When the polarity reversal is 1 or High, the 'tortoise pressure generation time kneel 507) in Fig. 7 is zero potential, (1--) Vop or output leaks, and the output from the circuit 66 in Fig. 8 is zero. is Vop.

(1--) Since the Vop output decreases, the 7JO torque for the liquid crystal (common '
Successful output change fluctuation and segment storm sliding door output (potential difference)
The polarity of will be reversed.

In Figure 10, the two frames exchanged! 4! , 1i110,000 ceremony #Kin is shown. Here, the number of eclipses (common “
Gold is shown when there are 12 electrodes a). 55 is the common Amegoku output Makikata, 54 is the modified segment output when all the lights are on, 55 is the segment Kagokokuta 7J Atsushi form when it is all clear, and b6 is the lighting and clearing appear alternately. 57 is the voltage waveform applied to the liquid crystal when all the lights are on, 58 is the voltage wave form of the 7JO voltage when all the lights are on, and 59 is the case where the lights on and off appear alternately. The liquid crystal application's sleep pressure is changed.

[One point while the invention is about to be decided]

However, the conventional Tainamink sitting method has a very low running speed.
Shu no Dan 7JQ With VC, poor autopsy display contrast occurs between the bite and the rise. For example, when a number of text characters are displayed, and in a two-frame, single-frame drive system, crosstalk often occurs on the display signal line between the displayed text characters. Further, a crosstalk phenomenon occurs in which lit pixels are concentrated on one display signal line, and unlit pixels on the display signal line appear to be lit.

These phenomena occur because, as is clear from h7, 58 and 59 in FIG. 10, the frequency of polarity reversal during the non-tracing time of the voltage waveform applied to the liquid crystal varies greatly depending on the display content.

Several methods have been proposed to solve these problems.

First, there is a method of increasing the frame frequency. However, because there is a limit to the drive frequency of the LCD controller IC,
The frame frequency cannot be increased enough to eliminate the crosstalk phenomenon. Also, the liquid crystal (:! MQ8 circuit sake 511
Since m is determined by the light emission tX flow at the time of switching, the flow of γ becomes difficult.

The other method uses black ink to lower the resistance of the membrane, but has the disadvantage that if the membrane that lowers the resistance is made thicker, the transmittance decreases.

It is also possible to develop a liquid crystal with less dependence on drive waveform frequency, but this has not yet been realized.

Therefore, in order to solve these conventional drawbacks, this invention
[Means for Solving the Problem] In order to solve the above problem, this invention aims to provide a liquid crystal display device with no display unevenness caused by crosstalk phenomenon. The inversion frequency is 6 times or more and 7 times or less than the frame direction, the polarity changes every frame, and AC driving is performed to eliminate display unevenness caused by crosstalk.

[Effect]

By using the dynamic driving method as described above, the polarity reversal frequency of the voltage applied to the liquid crystal when no electrode is selected does not vary greatly depending on the display content, so display unevenness in the liquid crystal display device can be eliminated.

〔composition〕

Therefore, the present invention will be explained below based on detailed illustrated embodiments.

FIG. 1 shows a liquid crystal display panel according to the present invention, with reference numeral 1 in the figure.
．． 2 is a substrate constituting a cell of a liquid crystal display panel, and a common electrode 1a,
2. A is provided, an insulating thin film of polyimide, Teflon, etc. is formed on the surface by printing or dipping, and a uniaxial orientation j%lb, 2t) is provided by rubbing in one direction.

The substrates 1.2 are arranged in parallel with their orientation surfaces facing each other and with four corners of several to several tens of microns, and liquid crystal is injected into the gap formed by the two substrates. Polarizing plates 3 and 4 are disposed on the upper and lower substrates formed in this way, respectively, with their polarization axes perpendicular to each other, and a display panel is constructed in such a way that the two positional states of liquid crystal molecules are displayed as bright and dark states. 0 FIG. 2 shows an embodiment of a liquid crystal display device using the above-mentioned liquid crystal panel, and reference numeral 6 in the figure is the above-mentioned liquid crystal display panel, with common electrodes and segment electrodes.
Each of them is configured by connecting a common electrode drive circuit 7 and a segment electrode drive circuit 8.

Next, these drive circuits will be explained.

FIG. 5 shows an embodiment of a common electrode drive circuit, and reference numeral 9 in the figure is a shift register, in which the aI@next scan signal is sequentially transferred by a clock signal synchronized with the common electrode scan speed. olo, which is used for shifting, is a latch circuit that latches the signal from the shift register 9 in synchronization with the clock signal, and outputs the drive voltage from the operating voltage generation circuit 11 (described later) to the common electrode CMI via the output gate circuit 12.
.

C"2 e...cMn. 11 is the aforementioned drive voltage generation circuit, and the liquid crystal drive voltage Vop, (+ --) supplied from a power supply (not shown).
Vop, -Vop.

a a 1 and zero potential, respectively, by analog switches Il&, 11b, ttc, such as gates.

11d, and receives the liquid crystal drive voltage Vop and zero voltage.

The outputs of the analog switches Ilc and 1+d which receive the supply of (1--)Vop and -Vop are output as a pair to the output gate 12, which will be described later.

Reference numeral 15 denotes a l/N frequency divider which divides the frequency of the clock aX and outputs a signal having a frequency 6 to 7 times the frequency of the polarity inversion signal. 14 is an exclusive OR gate, and a frequency divider 15
No. 48 and a polarity inversion signal are input, and when the polarity inversion signal is input, the signal phase from the frequency divider 13 is inverted, and the analog switch 11a forms a pair of the drive voltage generation circuit 11 directly and via the inverter 15. , 11b, and tic, 1
11i rule N? Input to a and drive voltage generation circuit +1
7)・ra zero potential and (1--)Vop or VOp
Output and -Vop a
a. Reference numeral 12 denotes an output gate consisting of a pair of two analog switches +2a and 12b, each of which receives a voltage supply from the drive voltage circuit 11.One analog switch 12a receives the output signal from the latch circuit 10 directly, and the other The signal is inverted by an inverter 16 and input to the analog switch 12b.

Figure '84 shows the actual segment electrode drive circuit ηjI described above.
In the figure, reference numeral 18 denotes a shift register, which is configured so that the data signal and the segment' sleeper scan timing, that is, the sub-scanning clock cx2, is input manually, and the data signal is shifted by the clock cx2. has been done. Reference numeral 19 denotes a latch circuit that latches the signal from the shift register 8 in synchronization with the clock signal cKz, and outputs a drive voltage from a drive voltage generation circuit 20 (described later) via a gate circuit 21 to generate a segment voltage m SGlm SG2 +
...Contains what is supplied to SGm. Reference numeral 20 denotes the aforementioned drive voltage generation circuit, which is a liquid crystal drive voltage supplied from a power supply (not shown). Op.

(') v' p+ -vOpe and zero potential, respectively, are transferred to analog switch 20a such as a transmission gate.

2ob, 20c, and 20d, and analog switches 20a and zob that receive the liquid crystal drive voltage Vop and zero potential, and (+--) 17op.
, -Vop, the outputs of analog switches 20c and 20 (L) are output as a pair to an output gate 21, which will be described later.

22 is a 1/N frequency divider, 23 is an exclusive OR gate,
j, respectively, have the same function as 13.14 in Fig. 5.

When the polarity inversion signal is input, the 1g phase of the frequency divider 22, 1, etc. is inverted, and the analog switches 20a, 2 forming the driving voltage generating circuit 200 pair are connected via the @ contact and the inverter 24.
Input to the control terminals of 0b, 20c, and 20d to output the zero potential and -Vop% signal from the drive voltage generation circuit 20.
p and (1--)Vop

It is configured to output a. 21 is an output gate made up of a pair of two analog switches 21a and 21b;
One analog switch 21a receives the output signal from the latch circuit 19, and the other analog switch 211) K4'! It is inverted and inputted from the inverter 25.

Next, the operation of the apparatus 7c constructed in this way will be explained based on the diagram of the limb shape shown in FIG. 45. In diagram 5g5, Hasikura line u,
12 Also, the frequency divider 15 in Figure 3 and the frequency divider 22 in Figure 44
The output frequency is six times the inversion No. 1g frequency.

When the line sequential scanning signal is output, it is latched by the latch circuit 10 via the shift register 9 and the common ' of the first flaw is output.
It and other CMs are in the selected state, and other common electrodes 0
'Jt°""'OM n is in the non-selected state. On the other hand, the clock OK+ is rounded by the frequency divider 16,
6X7 borrowing of polarity reversal number 100 frequency (arrow 7Ilf in Figure 5)
A signal of 6 borrowed frequencies is output from the gate and input to the exclusive sum gate 14. When the phase-displacement anti-private signal is input, the phase is inverted and the driving excitation pressure generation circuit l1611
Enter. Due to this signal, the common Denshen OMn receives the following voltage as an output. Figure 5 shows the detection force waveform of the output signal common in this way.

In the case of the segment circuit (FIG. 44), the output of the exclusive OR gate 25 is the same as the exclusive OR gate of FIG. This signal causes segment 1! Extreme S
The 'voltage' is output to Gm. The segment Effl output waveform in FIG. 5 is for the case where all the pixels are turned on.

In FIG. 5, the screw pressure applied to the liquid crystal is expressed as the difference between the output waveform of the controller 4jA and the segment output, and the liquid crystal is also moved by this coordinating pressure.

FIG. 6 shows an example of driving waveforms in the liquid crystal display device of the present invention. Here, a case is shown in which the number of common electrodes is 12. 46 is a common electrode, output waveform, 47 is a segment single pole output waveform when all lights are on, 48 is a segment formation seed output waveform of J in the case where all lights are off, 49 is a light on and clear alternately The segment electrode output waveform of the field that appears, 50
51 is the voltage waveform applied to the liquid crystal when all the lights are on, 51 is the waveform of the plate pressure applied to the liquid crystal when all the lights are off, and 52 is the waveform of the voltage applied to the liquid crystal when the lights are on and clear.

[Effects of the Invention] As described above, according to the present invention, two substrates each having a running pole and an alignment film on their surfaces are made with the alignment film side facing each other, and a liquid crystal compound is injected into the liquid crystal. When the panel is configured, the polarity reversal of the voltage applied to the liquid crystal when no electrode is selected is between 6 and 7 times the frame frequency, and the polarity changes every frame.
, since AC drive is used, it is possible to eliminate the distortion caused by crosstalk.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a device showing one embodiment of the liquid crystal panel used in the present invention, FIG. 2 is a view showing the structure of the liquid crystal display device of the present invention, and FIGS. , FIG. 5.6 is a block diagram showing an example of the common electrode ff1m circuit and the segment electrode drive circuit in the same device as above, respectively.
A waveform diagram showing the operation of the above device and FIG. 7.8 are a common electrode drive circuit and a segment x in the prior art, respectively.
FIG. 9.10 of an embodiment of the polar g motion circuit is a waveform chart showing the operation of the drive circuit of the prior art same as above. 1a...Common electrodes 1b, 2b...-axis alignment film 2a...Segment electrode 6...Liquid crystal panel 7...Common electrode drive circuit 8...Segment electrode drive circuit and above

Claims (2)

[Claims] (1) Two substrates with scanning electrodes and alignment films on their surfaces are placed with the alignment film sides facing each other, a liquid crystal compound is sealed between the substrates, and electrode selection is performed every time when all scanning lines are scanned once. In a liquid crystal display device that drives a liquid crystal by reversing the polarity of an applied voltage, the polarity reversal frequency of the voltage applied to the liquid crystal when no electrode is selected is 6 times or more the frequency (frame frequency) at which all scanning lines are scanned once, and 7 times or more. A liquid crystal display device characterized in that it is less than twice as large. (2) The liquid crystal display device according to claim 1, wherein the voltage applied to the liquid crystal when the non-electrode is selected changes polarity every time all scanning lines are scanned once, and AC driving is performed. .