JPH103069A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken the response which a liquid crystal moves from the on state to the off state. SOLUTION: When a scanning pulse is impressed on a scanning line G1 and a transistor 10 is turned on, picture data from a signal line D1 is inputted to the transistor 10 and also the data are held on a holding capacitance 20 and also a transistor 30 is turned on. When the transistor 30 is turned on, a voltage corresponding to the picture data is impressed on a display electrode 50 and liquid crystal is driven according to an AC voltage to be impressed on a counter electrode. At this time, when the level of the picture data is changed from an H to an L in a process in which a transistor 40 is turned on periodically according to a timing signal, electric charges accumulated on the liquid crystal capacitance between the display electrode 5 and the counter electrode is initialized to be zero in a timing when the transistor 40 is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device suitable for use as a low power consumption TFT active matrix liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display device, for example,
JP-A-7-271329, JP-A-6-24274
No. 9, published by Shunsuke Kobayashi, “Color Liquid Crystal Display” (industrial book), and the like are known. TFT (Thin Film Tra) among liquid crystal display devices
In a TFT active matrix type liquid crystal display device using an nistor, a line-sequential scanning method is employed as a driving method. In the line sequential scanning method, a scanning pulse is applied to each scanning electrode once every one frame time. On the other hand, a liquid crystal driving voltage is simultaneously applied to each signal electrode in synchronization with the scanning pulse, and the liquid crystal driving voltage is simultaneously applied to the liquid crystal of one row of pixels to which the scanning pulse is applied. I have. A frame time of about 1/60 second is often used, and this pulse is usually applied to each scanning electrode while sequentially shifting the timing from the upper side to the lower side of the panel. Therefore, as a pixel configuration, in a color panel of 640 × 480 dots, since one pixel is composed of three dots, the total number of dots is 1920 × 480 dots, and 48 pixels in one frame.
Since zero scanning electrodes (gate wirings) are scanned, the time width of the scanning pulse is about 35 μs. Then, in the selected pixel to which the liquid crystal driving voltage is applied in synchronization with the scanning pulse, the voltage of the gate electrode of the TFT connected to the scanning electrode increases, and the TFT is turned on. At this time, the liquid crystal drive voltage is applied to the display electrode via the source and drain of the TFT. As a result, the pixel capacitance obtained by combining the liquid crystal capacitance formed between the display electrode and the counter electrode and the load capacitance arranged in the pixel is charged. By repeating this operation, the liquid crystal drive voltage is repeatedly applied to the pixel capacitance on the entire panel every frame time.

Since an AC voltage is required to drive the liquid crystal, a voltage whose polarity is inverted every frame time is applied to a signal electrode. Therefore, for a frame frequency of 60 Hz, the driving frequency of the liquid crystal is 30 Hz which is a half of this frequency.
A flicker called flicker is visible, making the display difficult to see. Therefore, a driving method of alternately inverting the polarity of the liquid crystal driving voltage for each of the vertically and horizontally adjacent pixels is adopted, and by using this driving method, it is possible to obtain a good display with no noticeable flicker. . Note that 64
In the case of a panel of 0 × 480 dots, the polarity of the signal electrode is
Since it is inverted every 35 μs in one scanning period, the driving period of the signal electrode is 14.4 kHz, which is about 500 times the liquid crystal driving frequency.

[0004]

In the prior art, the capacitance at the intersection of the wiring (scanning electrode line, signal electrode line) of the scanning electrode and the signal electrode is determined by the difference between the wiring and the counter electrode formed over the entire surface of the counter substrate. A large amount of power is consumed because the charge and discharge of the intervening liquid crystal is repeated by the scanning pulse every frame time.

Accordingly, the applicant of the present application has filed Japanese Patent Application No. 8-629.
No. 96 proposes a liquid crystal display device in which power consumption is reduced. This liquid crystal display device includes a display data holding circuit that takes in display data based on a signal from a scanning electrode and display data from a signal electrode, and holds the display data. According to this device, since the display data holding circuit holds two values of "1" and "0" as the display data, a scanning pulse is applied for each frame when there is no change in the contents of the display data. It is no longer necessary to reduce power consumption.

However, in the above-described liquid crystal display device, the voltage applied to the liquid crystal is set to 0 by turning off the TFT element constituting the switching means, so that the voltage response when the TFT element is turned off from on is time. Or the voltage may fluctuate in the off state, which is an obstacle to improving image quality. Usually TF
When the T element is turned off from on, some voltage is applied to the liquid crystal. This voltage is held by the capacitance of the liquid crystal, and is gradually attenuated by the volume resistance of the liquid crystal and the resistance of the TFT element. As a result, if the voltage at which the TFT element shifts from on to off is held in the liquid crystal, the response of the liquid crystal applied voltage from on to off is extremely slow, making it difficult to display a moving image. In addition, since the response voltage changes depending on the volume resistance of the liquid crystal applied voltage in the off state and the leak current of the TFT element, the liquid crystal applied voltage in the off state becomes unstable.

An object of the present invention is to provide a liquid crystal display device capable of increasing the response when the voltage applied to the liquid crystal changes in accordance with image data.

[0008]

In order to achieve the above object, the present invention provides a liquid crystal layer including a liquid crystal constituting a plurality of pixels and at least one of the liquid crystal layers disposed opposite to each other with the liquid crystal layer interposed therebetween. A pair of transparent substrates, a plurality of scanning lines that are arranged on one of the pair of substrates and transmit the scanning pulse, and the plurality of scans are arranged and distributed on any one of the pair of substrates. A plurality of signal lines that intersect the lines in a matrix and transmit image data, an AC voltage generating means for generating an AC liquid crystal driving voltage, and a timing signal synchronized with the liquid crystal driving voltage generated from the AC voltage generating means are periodically transmitted. And a timing signal generating means for generating a plurality of scanning lines and a plurality of signal lines, and a plurality of display areas each surrounded by a plurality of scanning lines and a plurality of signal lines. Display electrode A counter electrode to which a liquid crystal driving voltage is applied from an AC voltage generating means, which is disposed opposite to each other, a pixel driving switching element connected to the display electrode, and a signal line from the signal line in response to a scanning pulse from the scanning line. Data holding means for holding the image data and controlling the switching operation of the pixel driving switching element in accordance with the held image data, and being applied between the display electrode and the counter electrode in response to a timing signal from the timing signal generating means The liquid crystal display device has an initializing means for initializing a voltage.

In configuring the liquid crystal display device, reset means for short-circuiting the pixel driving switching element in response to a timing signal from the timing signal generating means may be provided instead of the initializing means, or the data holding means may be provided. Logic means for controlling the pixel drive switching element to be in an on state in response to either the held pixel drive image data or the timing signal from the timing signal generation means may be provided.

In configuring each of the liquid crystal display devices, the following elements can be added.

(1) The switching element for driving the pixel is TF
A signal for spinning is input to a gate terminal, a drain terminal is connected to a display electrode, a source terminal is connected to a reference line indicating an average voltage of a liquid crystal driving voltage, and a timing signal generating means is provided. The timing signal is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates the average voltage.

(2) The switching element for driving the pixel is TF
A signal for spinning is input to a gate terminal, a drain terminal is connected to a display electrode, a source terminal is connected to a reference line indicating an average voltage of a liquid crystal driving voltage, and a timing signal generating means is provided. The timing signal is generated in synchronism with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates the average voltage, and stops at the timing when the voltage applied between the display electrode and the counter electrode becomes zero. Become.

(3) The pixel driving switching element is TF
A signal for spinning is input to a gate terminal, a drain terminal is connected to a display electrode, a source terminal is connected to a reference line indicating an average voltage of a liquid crystal driving voltage, and a timing signal generating means is provided. The timing signal is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates a voltage different from the average voltage, and stops at the timing when the liquid crystal driving voltage generated from the AC voltage generating means indicates the average voltage. Do it.

(4) The switching element for driving the pixel is TF
A signal for spinning is input to a gate terminal, a drain terminal is connected to a display electrode, a source terminal is connected to a reference line indicating an average voltage of a liquid crystal driving voltage, and a timing signal generating means is provided. The timing signal is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates a voltage different from the average voltage, and is generated at the timing when the voltage applied between the display electrode and the counter electrode becomes zero. Stop it.

(5) The pixel driving switching element is TF
A gate element for inputting image data, a drain terminal connected to a display electrode, a source terminal connected to a reference line indicating an average liquid crystal driving voltage, It is composed of a TFT element connected in parallel with the element, the gate terminal is connected to the timing signal generating means, the drain terminal is connected to the display electrode, and the source terminal is connected to the reference line indicating the average voltage of the liquid crystal drive voltage. I have.

(6) In the liquid crystal driving voltage generated from the AC voltage generating means, a period showing an average voltage equal to the average value of the alternating current is set every half cycle for a predetermined period.

According to the above-described means, the voltage applied between the display electrode and the counter electrode is initialized in response to the periodically generated timing signal, the element driving switching element is short-circuited, or Since the pixel drive switching element is controlled to be in an on state, the voltage applied to both ends of the liquid crystal capacitor can be periodically initialized to 0 voltage, and the liquid crystal applied voltage changes from on to off. Sometimes, the response can be hastened, and a good moving image or still image can be displayed as an image. Furthermore, when a still image is displayed as an image, power consumption can be reduced by lengthening the initialization cycle.

[0018]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a liquid crystal display device according to an embodiment of the present invention. In FIG. 1, the liquid crystal display device is a TFT active matrix type liquid crystal display, and includes a pixel circuit 100, a display unit 110, and a signal circuit 20.
0, scanning circuit 300, AC voltage circuit 400, timing circuit 500, center voltage circuit 600, counter substrate 700, T
The pixel circuit 10 includes an FT substrate 800,
0, display unit 110, signal circuit 200, scanning circuit 300,
The counter substrate TFT substrate 800 is formed on the color panel P. In the present embodiment, only the color panel P and its peripheral circuits are shown, and a specific structure of the color panel P such as an optical system is omitted.

The color panel P is provided with a counter substrate 700 and a TFT substrate 800 as a pair of substrates, each of which is opposed to each other with a liquid crystal layer (not shown) including liquid crystal constituting a plurality of pixels therebetween. Are located. And the counter substrate 7
Reference numeral 00 denotes a transparent substrate on which a transparent electrode is formed on one surface. The pixel circuit 10 is provided on the TFT substrate 800.
0, a display section 110, a signal circuit 200, and a scanning circuit 300 are formed. The pixel circuit 100 has n ×
m (n rows and m columns) are formed.
Scanning lines G1 to Gn are distributed and wired, and m signal lines D1 to Dm are arranged in a matrix with each scanning line.
Are distributed and wired. On the display surface of the color panel P, a plurality of display areas A11 to Anm, which are respectively surrounded by the scanning lines G1 to Gn and the signal lines D1 to Dm, are formed in a display section 110 that forms a display area. In this case, assuming that the number of scanning lines is 640 and the number of signal lines is 480, the color panel P is 640 × 4
An 80-dot panel is formed. In each display area, an AC signal line CP, a timing line TMG, and a reference line CNT are wired. The AC signal line CP is connected to the AC voltage circuit 400, the timing line TMG is connected to the timing circuit 500, and the reference line. CNT is the center voltage circuit 6
00 respectively.

Pixel circuit 100 formed in each display area
Is configured to include a data holding circuit 120 and a pixel control circuit 130, as shown in FIG. The data holding circuit 120 includes a transistor 10 formed of a TFT and a holding capacitor 20, and includes a pixel control circuit 130
Are provided with transistors 30, 40, display electrodes 40, and transparent electrodes 70 each formed of a TFT. When the pixel circuit 100 is an n-th row and m-th column pixel circuit,
The gate of the transistor 10 is connected to the scanning line Gn, the drain is connected to the signal line Dm, and the source is connected to the gate of the transistor 30 and one end of the storage capacitor 20.
The other end of the storage capacitor 20 is connected to the reference line CNT. The transistors 30 and 40 are connected in parallel with each other, the drain and the source are connected to each other, each drain is connected to the display electrode 70, and each source is connected to the reference line CNT. The gate of the transistor 40 is connected to the timing line TMG. A liquid crystal capacitor CLC is formed between the display electrode 50 and the counter electrode 70, and the counter electrode 70 is connected to the AC signal line CP.

The transistor 10 is turned on when the level of the scanning pulse applied to the scanning line Gn is "H",
Image data transmitted to the signal line Dm is taken in, a voltage Vdata according to the image data is applied to the gate of the transistor 30, and the storage capacitor 20 holds the voltage Vdata. That is, the data holding circuit 120 is configured as data holding means. Transistor 30
Is turned on when the level of Vdata is "H", and is configured as a pixel driving switching element for applying the voltage held in the holding capacitor 20 to the display electrode 50. The transistor 40 is turned on when the level of the timing signal transmitted on the timing line TMG is “H”, and short-circuits between the drain and source of the transistor 30. When the transistor 30 is off, the display electrode 50 and the counter electrode are turned off. An initializing means for initializing the voltage between 70 to 0 V or a reset means for short-circuiting between the drain and source of the transistor 30 is constituted. In addition, the signal circuit 2
Reference numeral 00 denotes an image data generating means for applying image data to each of the signal lines D1 to Dm.
Are configured as scanning pulse generating means for sequentially applying a scanning pulse to each of the scanning lines G1 to Gn.

Next, specific configurations of the AC voltage circuit 400, the timing circuit 500, and the center voltage circuit 600 will be described with reference to FIGS.

The timing circuit 500 includes monostable multivibrators 501, 502, 503, flip-flop 504, OR gate 505, inverter 506,
507, and AND gates 508 and 509. A synchronization signal VS synchronized with a signal defining a frame period is input to an input terminal of the timing circuit 500, and a timing signal VTMG of 60 Hz is output from an output terminal.
Is output periodically.

When the synchronization signal VS is input to the vibrator 501, the output terminals A, B, and C of the vibrators 501, 502, and 503 output the respective input signals as shown in FIGS. In response to the rising edge of the pulse, each multivibrator sequentially outputs a pulse having a designated pulse width. That is, each multivibrator 501-5
From 03, pulses delayed by the pulse width of each output pulse are sequentially output, and each pulse is input to the OR gate 505. Therefore, the OR gate 505 outputs a pulse from the output terminal D according to the logical sum of each pulse as shown in FIG.

On the other hand, the output pulse of the vibrator 501 is input to the flip-flop 504, and the output terminal E of the flip-flop 504 outputs a pulse having a pulse width as shown in FIG. That is, the flip-flop 504 performs an operation of inverting the output at the rising edge of the synchronization signal VS, and sequentially outputs a pulse whose logic is inverted every time the synchronization signal VS is generated. The output pulse of the flip-flop 504 is output to the AND gate 50.
8 and A through the inverter 506
Input to ND gate 509. AND gate 50
The output pulses of the OR gate 505 are input to the other input terminals of the inverters 8 and 509 via the inverter 507.
Therefore, a pulse according to the logical product of the output pulse of the flip-flop 504 and the output pulse of the inverter 507 is output from the output terminal F of the AND gate 508, and A
From the output terminal G of the ND gate 509, the inverter 506
Is output according to the logical product of the output pulse of the inverter 507 and the output pulse of the inverter 507. The output pulses of the output terminals D, F, and G are respectively applied to the AC voltage circuit 400
Has been entered. That is, the timing circuit 500 is configured as timing signal generating means for periodically outputting a high-level pulse.

The AC voltage circuit 400 includes power supplies 401 and 40
2, and switches 403, 404, and 405, and a connection point between the power sources 401 and 402 is connected to a reference line CNT.
Connected to the power supply 601 of the center voltage circuit 600. The plus terminal of the power supply 401 is connected to the AC signal line CP via the switch 404, the minus terminal of the power supply 402 is connected to the AC signal line CP via the switch 405,
A connection point between the power supply 401 and the power supply 402 is connected to the AC signal line CP via the switch 403.

The switch 403 closes the contact when the level of the pulse from the output terminal D of the OR gate 505 is "H", and the switch 404 switches the output terminal F of the AND gate 508.
The switch 405 is configured to close the contact when the level of the pulse from the output terminal G of the AND gate 509 becomes “H” when the level of the pulse from the input terminal becomes “H”. ing. That is, the switch 403
When the contact of the switch 404 is closed, a signal of the reference voltage or the center voltage VCNT corresponding to the output voltage of the power supply 601 is output when the contact of the switch 404 is closed, as shown in FIG. A signal of the voltage VP to which the voltage of the power supply 401 is added is output, and when the contact of the switch 405 is closed, the voltage (negative voltage) V of the power supply 402 is output.
An N voltage is output.

That is, the AC voltage circuit 400 generates an AC voltage which applies an AC voltage VCP having a maximum value VP and a minimum value VN with respect to the center voltage VCNT as a liquid crystal drive voltage to the counter electrode 70, for example, an effective value 3V. It is configured as a means. Also, the center voltage V is applied to the AC voltage VCP.
A positive period of the voltage VP and a negative period of the voltage VN are set with CNT therebetween, and the timing signal VTMG is generated during the period of the center voltage VCNT.

Next, the operation of the pixel circuit 100 will be described with reference to the timing chart of FIG. Note that the cycle of the timing signal VTMG is set to 周期 of the cycle of the AC voltage VCP, and is set to “H” when the timing signal VTMG is at the center voltage. Further, the timing at which the voltage Vdata applied to the gate of the transistor 30 changes depends on the writing of the data holding circuit 120, and the phase of the voltage Vdata and the phase of the voltage VCP depend on the position of the pixel even if the respective voltages are synchronized. different. Therefore, an example in which data is switched at substantially the center of the timing signal VTMG will be described here.

First, a scanning pulse is applied to the scanning line Gn to turn on the transistor 10, to input image data from the signal line Dm, and to turn on the transistor 30 when the level of the voltage Vdata of the image data is "H". , The voltage Vpix of the display electrode 50 becomes the voltage VCNT of the reference line CNT. Therefore, the display electrode 50 and the counter electrode 70
The liquid crystal in between has an AC voltage VCP as the liquid crystal drive voltage VLC.
Is applied as it is. For this reason, as shown in FIG. 6, a saturation voltage VH (minimum liquid crystal transmittance) and a voltage (arrow A) of 0 V (maximum liquid crystal transmittance) are alternately applied to the liquid crystal as an effective liquid crystal drive voltage VLC. Then, the liquid crystal is turned on.

Next, when the level of voltage Vdata shifts from "H" to "L" and the level of timing signal VTMG is "L", transistor 30 is turned off from on and transistor 40 is turned off. Maintained in state. As a result, the display electrode 50 is opened in a DC manner, and the liquid crystal driving voltage VLC becomes zero. But,
A liquid crystal capacitor CLC is provided between the display electrode 50 and the counter electrode 70.
, The voltage when the transistor 30 is on is transiently held by the liquid crystal capacitor CLC. Therefore, the voltage Vpix is maintained at the center voltage VCNT, and the AC voltage VCP is applied to the liquid crystal.

Thereafter, the level of the voltage Vdata becomes "H".
Is changed to "L", the timing signal VTMG
Becomes "H", the transistor 40 is turned on. As a result, the display electrode 50 is connected to the reference line CNT, the electric charge charged in the transmission capacitance CLC of the liquid crystal is discharged, and the electric charge in the liquid crystal capacitance CLC is initialized to zero.
That is, the voltage between the display electrode 50 and the counter electrode 70 is initialized to 0 volt. As a result, the liquid crystal is immediately turned off, and even if an AC voltage is applied to the counter electrode 70 thereafter,
Since each of the transistors 30 and 40 is maintained in the off state, the charge of the liquid crystal capacitor CLC is maintained at 0,
The voltage Vpix of the display electrode 50 is equal to the voltage VC of the counter electrode 70.
It becomes equal to P. That is, the liquid crystal applied voltage VLC is maintained at 0 voltage, and the liquid crystal maintains the light-off state.

As described above, in the present embodiment, the transistor 40 is periodically turned on according to the timing signal VTMG, and when the voltage Vdata is "L", the charge stored in the liquid crystal capacitor CLC is periodically set to zero. Therefore, the response of the liquid crystal driving voltage VLC to the change in the voltage Vdata is increased, and even when a moving image or a still image is displayed according to image data, an image of the moving image or the still image can be displayed in a favorable state. .

In the above-described embodiment, the cycle of the timing signal VTMG corresponding to the cycle of the initialization is set to half the cycle of the voltage VCP applied to the common electrode 70, but the response delay of the liquid crystal drive voltage VLC is delayed. Can be lengthened within the allowable range. In this case, the waveform of the voltage VCP is at least when the level of the timing signal VTMG is “H”.
The center value or the intermediate value of CP may be set to voltage VCNT.

Although the cycle of the voltage VCP is set to 1/30 second, it can be set independently of the write timing of the data holding circuit 120. That is, the write cycle of the data holding circuit 120 differs depending on data and is not constant, but the cycle of the voltage VCP is set to a certain cycle. Moreover, the cycle of the voltage VCP is related to flicker and power consumption. Therefore, if the cycle of the voltage VCP is shortened,
Although power consumption increases, flicker due to flicker can be reduced by increasing the frequency of flicker.
Conversely, when the cycle of the voltage VCP is lengthened, flicker is noticeable, but the frequency for driving the liquid crystal is reduced, so that power consumption can be reduced.

Next, a second embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the timing signal VTMG
Of the timing signal VTMG shown in FIG.
Using a timing signal VTMG wider than the pulse width of
Even when the level of the voltage Vdata of the data holding circuit 120 is "L", the transistor 40 is turned on for a short period, and the liquid crystal applied voltage VLC is set to the voltage VL corresponding to the threshold value of the liquid crystal shown in FIG. It is.

Specifically, as shown in FIG. 8, as the timing circuit 500, OR gates 511 and 512 are provided instead of the OR gate 505 of FIG.
11, the output pulses of the multivibrators 502 and 503 are input, the OR gate 512 receives the output pulses of the multivibrators 501 and 502, and the flip-flop 504 receives the output pulses of the multivibrator 502.

When the timing circuit 500 having the above configuration is used, as shown in FIG. 9, the timing signal VTMG becomes "H" when the levels of the output terminals A and B become "H". The AC voltage VCP has the maximum value VP when the output terminal F is “H”, and has the minimum value VN when the level of the output terminal G is “H”. That is, the timing signal VTMG is the center voltage VCNT of the AC voltage VCP.
Is set to "H" at a positive or negative timing.

In the above configuration, the data holding circuit 120
When the voltage Vdata becomes "H" and the transistor 30 is turned on, the voltage Vpxi of the display electrode 50 becomes the center voltage VCNT, the AC voltage VCP is applied to the liquid crystal as it is, and the liquid crystal is turned on.

Next, the voltage Vdata is changed from "H" to "L".
, And when the timing signal VTMG is "L", the transistors 30 and 40 are both turned off. At this time, the voltage Vpix is the center voltage VCNT, and the voltage VCP is applied to the liquid crystal. After this, the timing signal VT
When MG changes from “L” to “H”, transistor 4
When the voltage of the AC voltage VCP is at a level different from the voltage VCNT at this time, the voltage is applied to the liquid crystal as it is. And the timing signal VTM
When the level of the voltage VCP changes to the center voltage VCNT while G is in the “H” state, the display electrode 50 is connected to the reference line CNT, and the charge of the liquid crystal capacitance (transmission capacitance) CLC is initialized to zero. You.

Thereafter, when the timing signal VTMG periodically becomes "H" while the voltage Vdata is in the "L" state, the level of the AC voltage VCP becomes the center voltage VCP.
When the level is different from CNT, the transistor 40 is periodically turned on, and as shown by the arrow B in FIG. 6, the saturation voltage VH and the threshold voltage VL are used as the liquid crystal drive voltage VLC.
The liquid crystal is turned off in a state in which the voltage in the range is applied.

According to the present embodiment, the liquid crystal drive voltage VL
Since C is periodically initialized to 0 voltage, the response of the liquid crystal drive voltage VLC to a change in the voltage Vdata can be accelerated, and a favorable moving image or still image can be displayed. Further, even when the voltage Vdata is "L", a voltage in a range between the saturation voltage VH and the threshold voltage VL is applied to the liquid crystal as the liquid crystal drive voltage VLC, and therefore, the response of the liquid crystal is higher than in the above-described embodiment. The speed can be increased and the white balance can be adjusted by adjusting the threshold voltage VL for each color even when the display is adapted to a color display, thereby realizing a high-speed and high-quality liquid crystal display device. be able to.

FIG. 10 is a circuit diagram showing another embodiment of the pixel circuit 100 according to the present invention.

The pixel circuit 100 shown in FIG. 10 uses an OR gate 60 as a logic means instead of the transistor 40, the OR gate 60 is arranged on the gate side of the transistor 30, and one input terminal of the OR gate 60 is connected to the transistor. 10, the other input terminal is connected to the timing line TMG, and the output terminal is connected to the gate of the transistor 30.

In this embodiment, the OR gate 60
Is turned on when either the level of the voltage Vdata or the timing signal VTMG becomes “H”, and the same effect as when the pixel circuit 100 shown in FIG. 2 is used can be obtained.

Further, in this embodiment, the transistor connected to the display electrode 50 is only the transistor 30, and the transistor connected to the display electrode 10 is two.
Leakage current and noise can be reduced as compared with the case of the individual device, which can contribute to improvement of image quality.

In each of the above embodiments, the description has been given of the case where the center voltage VCNT is used as the voltage applied to the reference line CNT. However, the voltage applied to the reference line CNT is the average value of the AC voltage VCP. Equal average voltage,
A voltage of 0 V can be used.

When a still image is displayed in each of the above embodiments, the power consumption can be reduced by lengthening the initialization cycle.

In each of the embodiments, since the voltage corresponding to the threshold voltage VL and the saturation voltage VH in the liquid crystal drive voltage VLC can be set independently, a good color balance can be obtained when displaying a color image. it can. That is, when the amplitude value of the voltage VCP is changed, both the voltage corresponding to the saturation voltage VH and the voltage corresponding to the threshold voltage VL change. On the other hand, when the pulse width of the timing signal VTMG is changed, a voltage corresponding to the threshold voltage VL changes. Therefore, when Vdata is “H”, the voltage V
The amplitude value of CP is changed to match the saturation voltage of the liquid crystal. Next, when Vdata is "L", the pulse width of the timing signal VTMG is changed to match the voltage corresponding to the threshold value of the liquid crystal. be able to.

[0052]

As described above, according to the present invention,
Since the charge stored in the liquid crystal capacitor is periodically initialized to 0, the response speed can be increased when the liquid crystal drive voltage changes in accordance with the image data, so that moving images and still images can be displayed in good condition. Can be displayed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a pixel circuit.

FIG. 3 is a circuit configuration diagram of a timing circuit and an AC voltage circuit.

FIG. 4 is a timing chart for explaining the operation of the timing circuit and the AC voltage circuit.

FIG. 5 is a timing chart for explaining the operation of the pixel circuit.

FIG. 6 is a characteristic diagram showing a relationship between a liquid crystal driving voltage and a liquid crystal transmittance.

FIG. 7 is a timing chart for explaining the operation of another embodiment of the pixel circuit.

FIG. 8 is a circuit diagram showing another embodiment of the timing circuit.

9 is a timing chart for explaining the operation of the timing circuit and the AC voltage circuit shown in FIG.

FIG. 10 is a circuit diagram showing another embodiment of the pixel circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10, 30, 40 Transistor (TFT) 20 Storage capacity 50 Display electrode 60 OR gate 70 Counter electrode 100 Pixel circuit 200 Signal circuit 300 Scanning circuit 400 AC voltage circuit 500 Timing circuit 600 Center voltage circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Shoichi Hirota 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Masaya Adachi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Tatsuya Okubo 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. Visual Information Media Division

Claims (9)

[Claims] 1. A liquid crystal layer including liquid crystal constituting a plurality of pixels, a pair of substrates disposed opposite to each other with a liquid crystal layer therebetween, at least one of which is transparent, and one of the pair of substrates dispersed in one of the substrates. A plurality of scanning lines that are arranged and transmit scanning pulses, and a plurality of signal lines that are arranged dispersedly on one of the pair of substrates and intersect the plurality of scanning lines in a matrix and transmit image data. And AC voltage generating means for generating an AC liquid crystal driving voltage; and timing signal generating means for periodically generating a timing signal synchronized with the liquid crystal driving voltage generated from the AC voltage generating means. A plurality of display areas each surrounded by a plurality of signal lines, a display electrode disposed on one of a pair of substrates, and an AC voltage generating means disposed opposite to the display electrode with a liquid crystal layer interposed therebetween. LCD drive A counter electrode to which a voltage is applied, a pixel driving switching element connected to the display electrode, and pixel image switching in response to a scanning pulse from the scanning line and holding image data from the signal line in accordance with the held image data. A liquid crystal display comprising: a data holding unit for controlling a switching operation of an element; and an initialization unit for initializing a voltage applied between a display electrode and a counter electrode in response to a timing signal from a timing signal generation unit. apparatus. 2. A liquid crystal layer including liquid crystal constituting a plurality of pixels, a pair of substrates disposed opposite to each other with the liquid crystal layer interposed therebetween, at least one of which is transparent, and one of the substrates. A plurality of scanning lines that are arranged and transmit scanning pulses, and a plurality of signal lines that are arranged dispersedly on one of the pair of substrates and intersect the plurality of scanning lines in a matrix and transmit image data. And AC voltage generating means for generating an AC liquid crystal driving voltage; and timing signal generating means for periodically generating a timing signal synchronized with the liquid crystal driving voltage generated from the AC voltage generating means. A plurality of display areas each surrounded by a plurality of signal lines, a display electrode disposed on one of a pair of substrates, and an AC voltage generating means disposed opposite to the display electrode with a liquid crystal layer interposed therebetween. LCD drive A counter electrode to which a voltage is applied, a pixel driving switching element connected to the display electrode, and pixel image switching in response to a scanning pulse from the scanning line and holding image data from the signal line in accordance with the held image data. A liquid crystal display device comprising: a data holding unit that controls a switching operation of an element; and a reset unit that short-circuits a pixel driving switching element in response to a timing signal from a timing signal generating unit. 3. A liquid crystal layer including liquid crystal constituting a plurality of pixels, a pair of substrates disposed opposite to each other with the liquid crystal layer interposed therebetween, at least one of which is transparent, and one of the substrates. A plurality of scanning lines that are arranged and transmit scanning pulses, and a plurality of signal lines that are arranged dispersedly on one of the pair of substrates and intersect the plurality of scanning lines in a matrix and transmit image data. And AC voltage generating means for generating an AC liquid crystal driving voltage; and timing signal generating means for periodically generating a timing signal synchronized with the liquid crystal driving voltage generated from the AC voltage generating means. A plurality of display areas each surrounded by a plurality of signal lines, a display electrode disposed on one of a pair of substrates, and an AC voltage generating means disposed opposite to the display electrode with a liquid crystal layer interposed therebetween. LCD drive A counter electrode to which a voltage is applied, a pixel driving switching element connected to the display electrode, and pixel image switching in response to a scanning pulse from the scanning line and holding image data from the signal line in accordance with the held image data. A data holding unit for controlling a switching operation of the element; and a pixel driving switching element in an on state in response to one of the pixel driving image data held in the data holding unit and a timing signal from the timing signal generating unit. Liquid crystal display device each having a logic means for controlling the liquid crystal display device. 4. A switching element for driving a pixel is composed of a TFT element, a signal for swinging is input to a gate terminal, a drain terminal is connected to a display electrode, and a source terminal is a reference line indicating an average voltage of a liquid crystal driving voltage. 4. A liquid crystal display device according to claim 1, wherein the timing signal of the timing signal generating means is generated in synchronization with a timing at which a liquid crystal driving voltage generated from the AC voltage generating means indicates an average voltage. . 5. A switching element for driving a pixel is constituted by a TFT element, a signal for swinging is input to a gate terminal, a drain terminal is connected to a display electrode, and a source terminal is a reference line indicating an average voltage of a liquid crystal driving voltage. The timing signal of the timing signal generating means is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates the average voltage, and the voltage applied between the display electrode and the counter electrode. 4. The liquid crystal display device according to claim 1, wherein the generation is stopped at a timing when the value becomes zero. 6. A switching element for driving a pixel is constituted by a TFT element, a signal for swinging is input to a gate terminal, a drain terminal is connected to a display electrode, and a source terminal is a reference line indicating an average voltage of a liquid crystal driving voltage. The timing signal of the timing signal generating means is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates a voltage different from the average voltage, and the liquid crystal driving voltage generated from the AC voltage generating means is 4. The method according to claim 1, wherein the generation stops at a timing when the voltage indicates an average voltage.
The liquid crystal display device as described in the above. 7. A switching element for driving a pixel is composed of a TFT element, a signal for swinging is input to a gate terminal, a drain terminal is connected to a display electrode, and a source terminal is a reference line indicating an average voltage of a liquid crystal driving voltage. The timing signal of the timing signal generating means is generated in synchronization with the timing at which the liquid crystal driving voltage generated from the AC voltage generating means indicates a voltage different from the average voltage, and the timing signal is generated between the display electrode and the counter electrode. 4. The liquid crystal display device according to claim 1, wherein the generation is stopped at a timing when the applied voltage becomes zero. 8. A pixel driving switching element is composed of a TFT element, image data is input to a gate terminal, a drain terminal is connected to a display electrode, and a source terminal is connected to a reference line indicating an average voltage of a liquid crystal driving voltage. The reset means is composed of a TFT element connected in parallel with the pixel driving switching element, the gate terminal is connected to the timing signal generating means, the drain terminal is connected to the display electrode, and the source terminal is connected to the liquid crystal driving voltage. 3. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is connected to a reference line indicating an average voltage of the liquid crystal. 9. The liquid crystal driving voltage generated by the AC voltage generating means has a period in which an average voltage equal to the average value of the alternating current is set every half period for a predetermined period.
The liquid crystal display device according to 4, 5, 6, 7, or 8.