JPS6387924U - - Google Patents
Info
- Publication number
- JPS6387924U JPS6387924U JP18359286U JP18359286U JPS6387924U JP S6387924 U JPS6387924 U JP S6387924U JP 18359286 U JP18359286 U JP 18359286U JP 18359286 U JP18359286 U JP 18359286U JP S6387924 U JPS6387924 U JP S6387924U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock
- ring counter
- divide
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18359286U JPS6387924U (enExample) | 1986-11-28 | 1986-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18359286U JPS6387924U (enExample) | 1986-11-28 | 1986-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6387924U true JPS6387924U (enExample) | 1988-06-08 |
Family
ID=31130474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18359286U Pending JPS6387924U (enExample) | 1986-11-28 | 1986-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6387924U (enExample) |
-
1986
- 1986-11-28 JP JP18359286U patent/JPS6387924U/ja active Pending
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