JPS61160556U - - Google Patents
Info
- Publication number
- JPS61160556U JPS61160556U JP4258485U JP4258485U JPS61160556U JP S61160556 U JPS61160556 U JP S61160556U JP 4258485 U JP4258485 U JP 4258485U JP 4258485 U JP4258485 U JP 4258485U JP S61160556 U JPS61160556 U JP S61160556U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counter
- clock pulse
- inputs
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control By Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4258485U JPS61160556U (enExample) | 1985-03-25 | 1985-03-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4258485U JPS61160556U (enExample) | 1985-03-25 | 1985-03-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61160556U true JPS61160556U (enExample) | 1986-10-04 |
Family
ID=30553476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4258485U Pending JPS61160556U (enExample) | 1985-03-25 | 1985-03-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61160556U (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7360050B2 (en) | 1997-10-10 | 2008-04-15 | Rambus Inc. | Integrated circuit memory device having delayed write capability |
-
1985
- 1985-03-25 JP JP4258485U patent/JPS61160556U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7360050B2 (en) | 1997-10-10 | 2008-04-15 | Rambus Inc. | Integrated circuit memory device having delayed write capability |
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