JPS6386495A - Wiring board - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a wiring board on which semiconductor integrated circuit elements, particularly high-speed logic elements, are mounted.

(Prior Art) In recent years, in the field of semiconductor integrated circuit devices, there has been active development of high-speed logic devices such as GaAs (potassium arsenide) ICs that perform logic operations up to high-speed ranges. When a plurality of such high-speed logic elements are mounted on a mounting board and operated, the propagation delay and wiring capacitance of the wiring between the elements have a large effect on the overall logic operation speed.

The wiring structure of a normal multilayer board is shown in Figure 3, in which the top and bottom surfaces of the signal wiring are sandwiched between a ground plane or a conductive surface such as a power supply plane via an insulating layer in order to keep the characteristic impedance of the signal wiring constant. A wiring structure called a strip line, as shown in the figure, is often used.

In a wiring board having such a wiring structure.

One method for reducing the wiring capacitance is to use a low dielectric constant material for the insulating layer 42 surrounding the signal wiring 41. For example, alumina ceramic material (relative dielectric constant t ==9.s) and glass epoxy material (
ε, = 4.5), whereas polyimide material (t P-3,
8) or Teflon material (i P = 2.5).

Another method is to improve the wiring structure by patterning the conductor surface of the ground plane or power supply plane between the top and bottom of the signal wiring in a grid pattern, thereby lowering the signal wiring capacitance. be. FIG. 5(a) is a perspective view of such a wiring board seen from above.

A conductor surface 5 having a constant spatial period with respect to the signal distribution s51
3.54, the structure is sandwiched with an insulating layer 52 in between.

The upper and lower conductor surfaces 53 and 54 overlap each other in the same pattern.

However, when the ground plane or power supply plane is patterned into a grid pattern, when the signal wiring passes through the grid conductor plane,
A problem has arisen in that the characteristic impedance periodically fluctuates in response to the pitch of the grating, and the rougher the pitch of the grating, the larger the fluctuation value. That is, in FIG. 5(a), cross sections with different positional relationships such as cross sections AA' and BB' with respect to the signal wiring direction are shown in FIGS. 5(b) and 5(c).
The wiring capacitance between the signal arrangement 51 and the nearest conductor surface on the cross section AA' is CIA + C2A in the figure. On the other hand, in the cross section B-B', the wiring capacitance between the signal wiring 51 and the nearest conductor surface is 2 (CIB+Cza).
The wiring capacitance at A' and the cross section B-B' are different, and the characteristic impedance varies synchronously in accordance with the pitch of the lattice pattern.

High-speed logic elements such as GaAs IC have a smaller noise margin than other logic elements, such as TTL and ECL, so signal reflection due to changes in characteristic impedance can reduce the overall operating margin and cause logic malfunctions. , we had the good fortune to experience time fluctuations due to waveform distortion.

(Problems to be Solved by the Invention) As described above, the wiring structure having a patterned conductor surface for reducing wiring capacitance has a problem in that the characteristic impedance of the signal wiring fluctuates. An object of the present invention is to provide a wiring board having a wiring structure that suppresses fluctuations in signal characteristic impedance while using a patterned conductor surface.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above-mentioned objects, one aspect of the present invention is that signal wiring is formed by interposing an insulating layer between upper and lower conductor surfaces, which are shifted from each other by half the pattern period. This is a characteristic feature.

(Function) If the patterns on the upper and non-conductor surfaces are shifted from each other by half the pattern period as in the present invention, the pitch of variation becomes 172 in the signal wiring direction, and the distribution of wiring capacitance becomes uniform. The amount of variation in characteristic impedance is also reduced.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of the present invention.

The signal wiring 11 is sandwiched between an upper conductor surface 13 and a lower conductor surface 14, which are patterned in a lattice shape, with an insulating layer 12 in between. The material 1JL2 is made of an organic resin material such as polyimide material. The signal wiring 11 and the conductive surfaces 13 and 14 are made of a metal with good electrical conductivity such as copper. The upper and lower conductor surfaces 13, 14 are formed in a pattern with the same spatial repeating period, in this example a grid-like pattern.

At this time, the lattice points Q1 to Q4 on the lower conductor surface 14 are shifted by 172 of the repetition period (indicated by P in the figure) so that they are at the midpoint of the vertices of the lattice points P1 to P4 on the upper conductor surface. do. Regarding the present invention Cross section A-A' in the signal wiring direction
Comparing B-B' and B-B' results in b; as shown in Figure 1 (b) and (c), and just by reversing the positional relationship of the upper and lower conductors, the wiring capacitances are CIA + 202A and C2B + 2C2B.
are the same. Therefore, the characteristic impedance at the cross section AA' and the characteristic impedance at the cross section BB' are the same, and the period of variation of the characteristic impedance is 1/2. FIG. 2 shows the variation in characteristic impedance with respect to the cross-sectional position in FIG. 1.

In the case of the present invention (indicated by Ll in the figure), compared to the conventional case (indicated by Ll in the figure), the cross-sectional positions [A-A' and B-B
Since the characteristic impedances at ' are equal and the cross-sectional structures are the same at the midpoint c-c', Ll and L1 intersect at c-c'. Therefore, the period of fluctuation is essentially 1/
4, which greatly improves the variation.

FIG. 3 shows an embodiment in which the present invention is applied to a multilayer board, in which the signal wiring 31, 31' is connected to conductor planes 33, 34, 35 on the ground plane or power supply plane in multiple layers via absolute fa, 1132. It has a sandwiched structure. At this time, the conductor surface 33
, 34 and 35 are formed by shifting the pattern period by 1/2 from each other. 36 is an IC.

〔Effect of the invention〕

According to the present invention, variations in characteristic impedance are reduced by CC, which is formed by repeating patterns on conductor surfaces such as ground planes and power supply planes, which reduce wiring capacitance, and shifting patterns by a half of the period.

[Brief explanation of the drawing]

FIG. 1 is a perspective view and a cross-sectional view of a wiring board according to the present invention, FIG. 2 is a diagram comparing variations in characteristic impedance 2 between the present invention and a conventional example, and FIG. 3 is a diagram showing an embodiment of a multilayer board. Fourth
The figure shows a cross-sectional structure of a strip line, and FIG. 5 is a perspective view and a cross-sectional view of a conventional wiring board. 11.31, 41.51... Signal wiring, 12.32,
42.52...Insulating layer. 13.14, 33, 34, 53.54... Ground plane or power supply plane. Figure 1 Figure 2 Figure 3 Figure 4 <21> 5th v! J

Claims (1)

[Claims] In a wiring board having a structure in which signal wiring is sandwiched between conductive surfaces on the upper and lower surfaces with an insulating layer interposed therebetween, the upper and lower surfaces are formed of patterned conductors having almost the same constant period, and are shifted by half the period from each other. A wiring board characterized in that: