JPH0691324B2 - Wiring board - Google Patents

Description

Description: [Object of the Invention] (Industrial field of application) The present invention relates to a wiring board on which a semiconductor integrated circuit device, particularly a high-speed logic device is mounted.

(Prior Art) In recent years, in the field of semiconductor integrated circuit devices, high-speed logic devices such as GaAs (potassium arsenide) ICs that perform logic operations up to high-speed regions have been actively developed. When a plurality of such high-speed logic elements are mounted on a mounting board and operated, the propagation delay of the wiring between the elements and the wiring capacitance greatly affect the overall logic operation speed.

In order to keep the characteristic impedance of the signal wiring constant, the wiring structure of a normal multilayer board is shown in Fig. 3 in which the upper and lower surfaces of the signal wiring are sandwiched by a ground plane or a conductor plane such as a power plane through an insulating layer. In many cases, a wiring structure called a strip line as shown is adopted.

In a wiring board having such a wiring structure, as a method for reducing the wiring capacitance, one method is to use a low dielectric constant material for the insulating layer 42 surrounding the signal wiring 41. For example, alumina ceramic material (relative permittivity ε _r = 9.5) and glass epoxy material (ε _r = 4.5), polyimide material (ε _r = 3.8) and Teflon material (ε _r = 2.
5) etc. are to be used.

The other method is to devise a wiring structure by patterning the conductor planes of the ground plane or the power plane that sandwich the signal lines above and below to form a grid pattern to reduce the signal wiring capacitance. is there. FIG. 5 (a) is a perspective view of such a wiring board as seen from above, showing a structure in which the conductor surfaces 53 and 54 having a constant spatial period with respect to the signal wiring 51 sandwich the insulating layer 52. The upper and lower conductor surfaces 53 and 54 overlap each other in the same pattern.

However, when the ground plane or power plane is patterned in a grid pattern, when the signal wiring passes through the grid conductor surface,
The characteristic impedance periodically fluctuates corresponding to the pitch of the grid, and the coarser the pitch of the grid, the larger the fluctuation value. That is, FIGS. 5B and 5C show cross sections having different positional relations, such as cross sections AA ′ and BB ′ in the signal wiring direction in FIG. 5A. The wiring capacitance between the signal wiring 51 and the closest conductor surface at the cross section AA ′ is C _1A + C _2A in the figure. On the other hand, in the cross section BB ′, the wiring capacitance between the signal wiring 51 and the closest conductor surface is 2 (C _1B + C _2B ). Generally, the cross-section A-A 'and the cross-section B-B' have different wiring capacitances, and the characteristic impedance varies synchronously according to the pitch of the lattice pattern.

High-speed logic devices such as GaAs ICs can be replaced by other logic devices, such as TT
Since the noise margin is smaller than that of L or ECL, there are problems that signal reflection due to fluctuation of characteristic impedance causes a reduction in overall operation margin, logical malfunction, and time fluctuation due to waveform distortion.

(Problems to be Solved by the Invention) As described above, the wiring structure having the patterned conductor surface for reducing the wiring capacitance has a problem that the characteristic impedance of the signal wiring fluctuates. It is an object of the present invention to provide a wiring board having a wiring structure that suppresses fluctuations in signal characteristic impedance while using a patterned conductor surface.

[Structure of Invention]

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides that the signal wirings are formed with the insulating layer interposed therebetween so that the conductor surfaces sandwiched above and below are offset from each other by half the pattern period. It is a feature.

(Operation) When the patterns on the upper and lower conductor surfaces are shifted from each other by half the pattern period as in the present invention, the pitch of fluctuation becomes 1/2 with respect to the signal wiring direction, and the wiring capacitance distribution becomes uniform. In addition, the fluctuation amount of the characteristic impedance is also reduced.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of the present invention. The signal wiring 11 is
The upper conductor surface 13 and the lower conductor surface 14, which are patterned in a lattice pattern, are sandwiched by an insulating layer 12. The insulating layer 12 is made of an organic resin material such as a polyimide material. Signal wiring 11
Alternatively, the conductor surfaces 13 and 14 are formed of a metal having good electric conductivity such as copper. The upper and lower conductor surfaces 13 and 14 are formed in a pattern having the same spatial repeating period, in this example, a grid pattern. At this time, the grid points Q1 to
Q4 is formed by shifting by 1/2 of the repeating cycle (indicated by P in the figure) so that it is located at the midpoint of the vertex of the grid points P1 to P4 on the Jobu conductor surface. In the present invention, a cross section A- in the signal wiring direction
Comparing A ′ and BB ′ is as shown in FIGS. 1 (b) and (c), and the wiring capacities C _1A + 2C _2A and C _2B + 2C are obtained only by reversing the positional relationship between the upper and lower conductors. _2B will be the same. Therefore, the characteristic impedance in the section A-A 'and the section B-
The characteristic impedance in B'is the same, and the variation cycle of the characteristic impedance is 1/2. FIG. 2 shows the variation of the characteristic impedance with respect to the cross-sectional position of FIG.

In the case of the present invention (indicated by L1 in the figure) and in the conventional case (indicated by L2 in the figure)
Characteristic) at the cross-section positions AA ′ and BB ′ are equal to each other, and the intermediate point C
Since -C 'has the same sectional structure, L1 and L2 intersect at CC'. Therefore, the fluctuation period is substantially 1/4, and the fluctuation amount is greatly improved.

FIG. 3 shows an embodiment in which the present invention is applied to a multi-layer substrate, in which the signal wirings 31 and 31 'are connected to the ground plane or the conductor planes 33, 34 and 35 of the power plane through the insulating layer 32 to form a multi-layer. It has a sandwiched structure. At this time, the conductor surfaces 33, 34, and 35 are formed by shifting the pattern period from each other by 1/2. 36 is an IC.

〔The invention's effect〕

According to the present invention, the variation of the characteristic impedance is reduced by the CC formed by repeatedly forming the patterns having the repeating period on the conductor planes such as the ground plane and the power plane for reducing the wiring capacitance, by shifting the patterns by the half cycle.

[Brief description of drawings]

FIG. 1 is a perspective view and a sectional view of a wiring board according to the present invention, FIG. 2 is a view comparing variations of the characteristic impedance 2 of the present invention and a conventional example, and FIG. 3 is a view showing an embodiment of a multilayer board, Fourth
FIG. 5 is a view showing a cross-sectional structure of a strip line, and FIG. 5 is a perspective view and a cross-sectional view of a conventional wiring board. 11,31,41,51 …… Signal wiring, 12,32,42,52 …… Insulating layer, 13,14,33,34,53,54 …… Ground plane or power plane.

Claims (1)

[Claims] 1. A wiring board having a structure in which an upper surface and a lower surface are sandwiched by conductor surfaces with an insulating layer sandwiching a signal wiring, and the upper surface and the lower surface are formed of patterned conductors having substantially the same constant period, A wiring board characterized by being formed with a shift of half the cycle.