JPS6380606A - High frequency amplifying device - Google Patents
High frequency amplifying deviceInfo
- Publication number
- JPS6380606A JPS6380606A JP22662786A JP22662786A JPS6380606A JP S6380606 A JPS6380606 A JP S6380606A JP 22662786 A JP22662786 A JP 22662786A JP 22662786 A JP22662786 A JP 22662786A JP S6380606 A JPS6380606 A JP S6380606A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- conductor
- high frequency
- dielectric
- dielectric thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims abstract description 50
- 239000004020 conductor Substances 0.000 claims abstract description 47
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000003321 amplification Effects 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は小型かつ高利得な高周波増幅器に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compact and high-gain high-frequency amplifier.
高敵増幅器の利得を高める為には、複数の電界効果型ト
ランジスタＣＦ’ＥＴ ）を多段に接続する方法がとら
れる。多段のモノリシック増幅器を小型化する場合、隣
シ合わせのＦＥＴ間隔は非常に近くなり、ＦＥＴのソー
ス電極と接続される導体幅が狭くなるため、ソース接地
インダクタンスが増大し、高い周波数においては利得が
急激に低下する。また、複数のＦＥＴのソース電極に接
続される接地用導体を共有化して幅を広くしようとする
と、ＦＥＴのバイアス回路と必ず交差することになるが
、その場合、交差の構造を工夫しないと高周波特性が劣
化する。In order to increase the gain of the high efficiency amplifier, a method is used in which a plurality of field effect transistors CF'ET are connected in multiple stages. When miniaturizing a multistage monolithic amplifier, the spacing between adjacent FETs becomes very close, and the width of the conductor connected to the source electrode of the FET becomes narrower, which increases the common source inductance and reduces the gain at high frequencies. Declines rapidly. Also, if you try to increase the width by sharing the grounding conductor connected to the source electrodes of multiple FETs, it will inevitably intersect with the bias circuit of the FETs, but in that case, unless the crossing structure is devised, high frequency Characteristics deteriorate.
従来・２０ ＧＨｚ以上のモノリシック増幅器は、高々
、２段以下の構成であり、また、ことさら小型化を試み
なかったことがら、ソースの接地用導体幅は十分とれた
。しかし、半導体製造技術の進歩とともに、２０ ＧＨ
ｚ以上の超高周波でも小型集積化、高利得化が望まれる
ようになることは必至であり、その場合、いかにソース
接地インダクタンスを小さくするかが問題となろう。第
３図に、２４１ ＧＨｚにおけるモノリシックｊ段増幅
器（第≠図に回路図）の利得と各ＦＥＴのソース接地イ
ンダクタンスの関係を示す。インダクタンスは導体長に
比例し、導体幅に逆比例するからＦＥＴのソース電極に
接続される導体は短かく、かつ、幅が広い程良い。ソー
ス電極に接続される導体幅が３０μｍ。Conventional monolithic amplifiers of 20 GHz or higher have a configuration of at most two stages or less, and because no particular attempt was made to reduce the size, the width of the source grounding conductor was sufficient. However, with the advancement of semiconductor manufacturing technology, 20 GH
Even at ultra-high frequencies above z, it is inevitable that smaller integration and higher gain will be desired, and in that case, the problem will be how to reduce the source-grounded inductance. FIG. 3 shows the relationship between the gain of a monolithic J-stage amplifier (circuit diagram shown in the figure) and the common source inductance of each FET at 241 GHz. Inductance is proportional to the conductor length and inversely proportional to the conductor width, so the shorter and wider the conductor connected to the source electrode of the FET, the better. The width of the conductor connected to the source electrode is 30 μm.
長さを１００μｍあるものとし、それを直径２ｊμｍ１
長さ！００μｍ程度の金ワイヤで グラウンドに接地し
たとすると０．／ｎＨ程度のインダクタンスを持つ。こ
の条件を先の！段増幅器に適用すると理想的な接地が行
なわれた場合に比べ利得が約＆ ｄＢ低下する。これは
、出力にすると十になることを意味する。ソース接地イ
ンダクタンスを小さくする方法として、ＧａＡ、基板に
バイアホールをあけ裏面から接地する方法が現在とられ
ているが、接地スヘースが、２００Ｘ２００”−〜３０
０Ｘｊ００ 程度必要であり、小型化、高集積化に適し
ないばかシか、プロセス的にも信頼性は高いといえない
等の欠点があった。Assume that the length is 100μm, and the diameter is 2jμm1
length! If you connect it to the ground with a gold wire of about 0.00μm, it will be 0.00μm. It has an inductance of about /nH. This condition is first! When applied to a stage amplifier, the gain decreases by approximately &dB compared to when ideal grounding is performed. This means that the output will be 10. The current method of reducing the source grounding inductance is to drill a via hole in the GaA substrate and ground it from the back side.
It requires about 0Xj00, which is not suitable for miniaturization and high integration, and has disadvantages such as not being highly reliable in terms of process.
本発明の目的はこれらの欠点を除去するだめ、ソース電
極に接続される導体の幅を十分広くとることを可能にす
るとともに、この導体とバイアス回路との交差部分にキ
ャパシタを構成することによシ、高周波特性をさらに改
善するように構造を工夫した高周波増幅装置を提供する
ことにある。The purpose of the present invention is to eliminate these drawbacks by making it possible to make the width of the conductor connected to the source electrode sufficiently wide, and by configuring a capacitor at the intersection of this conductor and the bias circuit. Another object of the present invention is to provide a high-frequency amplification device whose structure is devised to further improve high-frequency characteristics.
裏面導体グラウンドの上にＧａＡ、基板を設け、ＧａＡ
Ｓ基板の上に下層導体薄膜を設け、下層導体薄膜の上に
誘電体薄膜と誘電体薄膜に穴をあけて埋め込んだバイア
メタルを設け、ソース電極と接続された上層導体薄膜と
同じ材料で形成した接地用導体部分は、バイアメタルで
下層導体薄膜に接続される。一方、上層導体薄膜と同じ
材料で形成したバイアス供給用パッド部分は、前記誘電
体薄膜上に設けられ、バイアス供給用パッド、誘電体薄
膜及び下層導体薄膜とで高周波ショートキャパシタを構
成する。A GaA substrate is placed on the back conductor ground, and the GaA
A lower conductor thin film is provided on the S substrate, a dielectric thin film and a via metal embedded in the dielectric thin film are provided on the lower conductor thin film, and are made of the same material as the upper conductor thin film connected to the source electrode. The grounding conductor portion is connected to the lower conductor thin film using a via metal. On the other hand, a bias supply pad portion formed of the same material as the upper conductor thin film is provided on the dielectric thin film, and the bias supply pad, dielectric thin film, and lower conductor thin film constitute a high frequency short capacitor.
このような構造にすると、ＦＥＴのソース電極に接続さ
れる接地用導体はバイアメタルを通じて全てのＦＥＴ間
で共有化される下層導体薄膜に接続されるとともに、導
体幅を増幅器全体の幅にまで広げることが可能である。With this structure, the ground conductor connected to the source electrode of the FET is connected to the lower conductor thin film shared among all FETs through the via metal, and the conductor width is expanded to the width of the entire amplifier. Is possible.
またバイアス供給用パッドと下層導体薄膜は誘電体薄膜
によりキャパシタを構成できる。これらに起因して、Ｆ
ＢＴのソース接地インダクタンスの増大を防ぐことがで
き、バイアス供給用パッドを高周波ショートキャパシタ
として使用できるので、外部電源回路の特性が高周波特
性に影響を与えることを防げる。Further, the bias supply pad and the lower conductor thin film can constitute a capacitor using a dielectric thin film. Due to these, F
Since it is possible to prevent the source common inductance of the BT from increasing and the bias supply pad can be used as a high frequency short capacitor, it is possible to prevent the characteristics of the external power supply circuit from affecting the high frequency characteristics.
第１図及び第２図は、本発明の実施例であって、／は接
地された裏面導体、コはガリウムひ素（ＧａＡ、 ）基
板、３は例えばモリブデン（Ｍｏ）、チタン（Ｔ１）等
を７０００λ 積層させた下層導体薄膜、≠は例えば、
ＳｉＮ膜又はＳｉｎ、膜をＪ″ｏｏ。1 and 2 show embodiments of the present invention, where / is a grounded back conductor, C is a gallium arsenide (GaA) substrate, and 3 is a substrate made of molybdenum (Mo), titanium (T1), etc. 7000λ laminated lower conductor thin film, ≠ is, for example,
SiN film or Sin film.
＾〜７０００人積層させた誘電体薄膜、夕は接地用導体
部であって、誘電体薄膜≠に穴をあけて例えばＡ、Ａの
ような金属を埋め込んだバイアメタル７によシ下層導体
薄膜３と接続されており、上層導体薄膜？例えば密着性
向上のためにＴｉ、Ｍｏ等を！ＯＱλ〜７０００人スパ
ッタしてからＡμを／μｍ蒸着させた上層導体薄膜と同
じ材料で形成されておシ、乙は前記上層導体薄膜ｔと同
じ材料で形成されたバイアス供給用パッドであり、接地
用導体部ｊは配線部ＩＱを通じて高周波増幅回路を構成
するＦＥＴ 、例えば第μ図のＰＥＴ ／〜ｊのソース
電極（図示せず）と接続され、バイアス供給相バッド乙
から引き出されたリード線りはＦＥＴのゲート（図示せ
ず）若しくはドレイン（図示せず）に接続されバイアス
を供給する。前記バイアメタル７はＰＥＴのソース電極
を多数の金ワイヤで接地した場合と同様の役目を果たす
。即ち、通常金ワイヤによるインダクタンスはその使用
本数に逆比例して減少するものであり、上述の実施例で
は、バイアメタル７の数に逆比例してそのインダクタン
スが減少する。従ってＦＥＴのソース電極は良好な接地
状態になる。一方、バイアス供給用パッド６と誘電体薄
膜≠と下層導体薄膜３によってキャパシタを構成してい
る。バイアス供給側パッド乙は外部電源回路に接続し、
下層導体薄膜３は接地される。^ ~ 7000 layers of dielectric thin film, and the grounding conductor part, and the lower layer conductor thin film is made by drilling a hole in the dielectric thin film≠ and filling it with a metal such as A, A via metal 7. 3 and is connected to the upper layer conductor thin film? For example, use Ti, Mo, etc. to improve adhesion! It is formed of the same material as the upper layer conductor thin film, which is sputtered for OQλ~7000 times and then evaporated with Aμ/μm. The conductor part j is connected to the source electrode (not shown) of the FET constituting the high-frequency amplification circuit through the wiring part IQ, for example, PET/~j in Fig. μ, and is connected to the lead wire drawn out from the bias supply phase pad B. is connected to the gate (not shown) or drain (not shown) of the FET to supply a bias. The via metal 7 plays the same role as when the source electrode of PET is grounded with a large number of gold wires. That is, the inductance of gold wires normally decreases in inverse proportion to the number of gold wires used, and in the above embodiment, the inductance decreases in inverse proportion to the number of via metals 7. Therefore, the source electrode of the FET is well grounded. On the other hand, the bias supply pad 6, the dielectric thin film≠, and the lower conductive thin film 3 constitute a capacitor. Bias supply side pad A is connected to the external power supply circuit,
The lower conductor thin film 3 is grounded.
このキャパシタは高周波増幅器側から見ると、外部電源
回路と並列に接続されることになる。例えば誘電体薄膜
をＳｉＮ若しくは５ｉｎｔで形成し、その厚さを０．５
μｍとして、バイアス供給用パッド６を１００／ｊｍ×
１００μｍ とするとキャパシタは／ 、Ｆ以上の容量
を持つが、これは１０ＧＨｚ以上の周波数の電波に対し
てショート回路として働く。従って、バイアス供給用パ
ッド６、誘電体薄膜弘、下層導体薄膜３で構成されたキ
ャパシタは外部電源回路と並列に接続された高周波ショ
ート回路となる。このことは、増幅器内の高周波からは
外部電源回路が見えなくなることと等しくなシ、増幅器
の高周波特性は外部電源回路の影響を受けなくなる。ま
た、高周波の外部電源への漏れがなくなることも同時に
意味する。When viewed from the high frequency amplifier side, this capacitor is connected in parallel with the external power supply circuit. For example, a dielectric thin film is formed of SiN or 5 int, and its thickness is 0.5
μm, bias supply pad 6 is 100/jm×
If it is 100 μm, the capacitor has a capacitance of /F or more, but this acts as a short circuit for radio waves with a frequency of 10 GHz or more. Therefore, the capacitor composed of the bias supply pad 6, the dielectric thin film 3, and the lower conductive thin film 3 becomes a high frequency short circuit connected in parallel with the external power supply circuit. This is equivalent to the fact that the external power supply circuit becomes invisible from the high frequency within the amplifier, and the high frequency characteristics of the amplifier are no longer influenced by the external power supply circuit. It also means that there is no leakage of high frequency waves to the external power supply.
第３図の黒の九点は本発明を用いて実際に製作したモノ
リッツ２！段増幅器の測定値を示す。各ＦＥＴのソース
電極から見える接地インダクタンスは０．０／ｎＨとな
っており、本発明を用いない時（白丸）の０．ＩｎＨに
比ベソース接地インダクタンスが １／１ｏ となシ、
従って利得が十分改善されていることが判る。The nine black dots in Figure 3 are the Monolitz 2 actually manufactured using the present invention! The measured values of the stage amplifier are shown. The ground inductance seen from the source electrode of each FET is 0.0/nH, which is 0.0/nH when the present invention is not used (white circles). Compared to InH, the source grounding inductance is 1/1o.
Therefore, it can be seen that the gain has been sufficiently improved.
以上説明したように、本発明を用いれば、高周波増幅器
の多段化によるＦＥＴのソース接地インダクタンスの増
大を防ぐことが可能となり、高周波でのソース接地イン
ダクタンスによる利得の低下を生じさせない。また、バ
イアス供給用バンドを高周波ショートキャパシタとして
使用できることになシ、増幅器の高周波特性に外部電源
回路の特性が入り込まないという利点がある。As described above, by using the present invention, it is possible to prevent an increase in the common source inductance of the FET due to multi-stage high frequency amplifiers, and a decrease in gain due to the common source inductance at high frequencies is not caused. Furthermore, since the bias supply band can be used as a high frequency short capacitor, there is an advantage that the characteristics of the external power supply circuit do not interfere with the high frequency characteristics of the amplifier.
第１図は増幅装置の本発明にかかわる部分の断面図、第
２図は斜め上方から見た本発明の解説図、第３図は２μ
ＧＨｚ帯ｊ段増幅器の利得に与えるＦＥＴのソース接地
インダクタンスの影響図、第μ図は２μＧＨｚ帯ｊ段増
幅器の等価回路である。
ハ・・接地された裏面導体、λ・・・ガリウムひ素基板
、３・・・下層導体薄膜、≠・・・誘電体薄膜、！・・
・接地用導体、６・・・バイアス供給用パッド、７・・
・ノ（イアメタル、♂・・・上層導体薄膜、り・・・リ
ード線、１０・・・配線部。Fig. 1 is a sectional view of the part of the amplifier device related to the present invention, Fig. 2 is an explanatory diagram of the present invention seen diagonally from above, and Fig. 3 is a 2μ
Figure μ, which is a diagram showing the influence of the common source inductance of an FET on the gain of a GHz band j-stage amplifier, is an equivalent circuit of a 2 μGHz band j-stage amplifier. C... Grounded back conductor, λ... Gallium arsenide substrate, 3... Lower layer conductor thin film, ≠... Dielectric thin film,!・・・
・Grounding conductor, 6...Bias supply pad, 7...
・ノ(ear metal, ♂...upper layer conductor thin film, ri...lead wire, 10...wiring part.
Claims (1)
て、下層導体薄膜上に誘電体薄膜と誘電体薄膜の一部に
穴をあけて埋め込んだバイアメタルを設け、前記誘電体
薄膜と前記バイアメタル上に上層導体薄膜を設けた構造
をもち、バイアス供給用パッドと接地用導体は前記上層
導体薄膜で形成され、前記バイアス供給用パッドは前記
誘電体薄膜上に設けられ、前記バイアス供給用パッドと
前記誘電体薄膜と前記下層導体薄膜とで高周波ショート
キャパシタを構成し、さらに前記バイアス供給用パッド
は前記電界効果トランジスタのゲート若しくはドレイン
に接続され、一方前記接地用導体は前記バイアメタルと
前記電界効果トランジスタのソース電極に接続されてい
ることを特徴とする高周波増幅装置。In a high frequency amplification device equipped with a field effect transistor or the like, a dielectric thin film and a via metal formed by making a hole in a part of the dielectric thin film are provided on a lower conductive thin film, and an upper layer is formed on the dielectric thin film and the via metal. It has a structure in which a conductor thin film is provided, a bias supply pad and a grounding conductor are formed of the upper layer conductor thin film, the bias supply pad is provided on the dielectric thin film, and the bias supply pad and the dielectric The thin film and the lower conductor thin film constitute a high frequency short capacitor, and the bias supply pad is connected to the gate or drain of the field effect transistor, while the ground conductor is connected to the via metal and the source of the field effect transistor. A high frequency amplification device characterized by being connected to an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22662786A JPS6380606A (en) | 1986-09-25 | 1986-09-25 | High frequency amplifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22662786A JPS6380606A (en) | 1986-09-25 | 1986-09-25 | High frequency amplifying device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6380606A true JPS6380606A (en) | 1988-04-11 |
Family
ID=16848156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22662786A Pending JPS6380606A (en) | 1986-09-25 | 1986-09-25 | High frequency amplifying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6380606A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259762A (en) * | 1992-03-10 | 1993-10-08 | Yokowo Co Ltd | High frequency circuit structure |
-
1986
- 1986-09-25 JP JP22662786A patent/JPS6380606A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05259762A (en) * | 1992-03-10 | 1993-10-08 | Yokowo Co Ltd | High frequency circuit structure |
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