JP2718405B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device forming a high-frequency amplification field-effect transistor.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor using gallium arsenide (hereinafter referred to as a GaAs FET) has been used as a high frequency amplifying element. Among them, a low noise amplifying element is widely used for receiving satellite broadcasts and the like. Have been. FIG.
Is GaAs for low-noise amplification as a conventional semiconductor device.
1 shows a configuration diagram of an example of an FET. FIG. 2A shows a GaAs for low noise amplification in a package with the cap removed.
FIG. 2B is a plan view showing a state where the FET chip is mounted, and FIG. 2B is a side view along the line aa ′ in FIG.

As shown in FIGS. 3A and 3B, a single-layer ceramic 1 is conventionally used as a package for the purpose of reducing package cost. 2 is an alumina coat,
3, 5, and 7 are external lead terminals of a source electrode, a gate electrode, and a drain electrode. The internal metallized patterns 4, 6 and 8 of the source electrode, the gate electrode and the drain electrode are
Connected by 0.

[0006] Internal metallized patterns 4 and 6 are connected to external lead terminals 3 and 5 by a source side metallization 11 and a gate side metallization 12 shown in FIG. Usually, the width of the side metallization pattern is the same as the width of the external lead terminal. Therefore, the width of the gate side metallization 12 is provided to be the same as the width of the lead terminal of the external gate electrode 5. I have.

In the conventional GaAs FET shown in FIG. 3, the number or length of the bonding gold wires 10 is usually adjusted to improve high-frequency characteristics or match input / output impedance.

As a method of matching input / output impedance in a conventional semiconductor device, for example, Japanese Patent Laid-Open No.
As described in JP-A-166815, a space is provided between the FET element and the microstrip substrate, the space therebetween is connected by a lead terminal of the FET element, and the inductance is changed by controlling the length of the lead terminal. There is known a method for facilitating impedance matching.

[0007]

However, FIG.
In the GaAs FET as a conventional semiconductor device shown in (1), in order to improve the high-frequency characteristics or facilitate the matching of the input / output impedance, the input / output inductance is changed by changing the number or length of the bonding gold wires 10. Although it is necessary to use the current GaAs FET for low noise amplification, the size of the FET chip 9 is 0.4 m.
m to about 0.5 mm square, and the outer shape of the package (ceramic 1) is ~ 1.8 mmφ and the inner diameter is ~
It is about 1.4 mmφ.

For this reason, in the conventional semiconductor device shown in FIG. 3, there is a limit in adjusting the length of the input / output bonding gold wire 10, and increasing the number of bonding wires is not advantageous in terms of cost reduction. There is a problem that it is difficult.

Japanese Patent Application Laid-Open No. Sho 58-166815 discloses a method of changing the length of an external lead terminal to achieve impedance matching. The influence of the length is extremely remarkable, the mounting accuracy on the microstrip substrate is severe, and it is extremely difficult to reduce the cost.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor device having improved gain characteristics while suppressing an increase in cost.

[0011]

According to the present invention, in order to achieve the above object, a field effect transistor chip in a package is connected to metallization patterns inside the package of source, gate and drain electrodes via bonding wires. In a semiconductor device in which each package internal metallization pattern is connected to the corresponding external lead terminal of the corresponding source electrode, gate electrode and drain electrode by the package side metallization pattern, the package side metallization pattern of the gate electrode and the gate electrode The internal metallized pattern is formed narrower than the external lead terminal width of the gate electrode.

According to the present invention, the input inductance including the internal metallized pattern of the gate electrode and the metallized pattern on the side surface of the package of the gate electrode can be used.
The gain can be set to a value that gives the optimum value. Here, it is preferable that the package is a single-layer ceramic and the field-effect transistor chip is a hetero-junction field-effect transistor for the above-mentioned optimal gain setting.

[0013]

Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of an embodiment of the present invention. FIG. 1A is a plan view showing a state in which a low-noise amplifying FET chip is mounted on a package with a cap removed, and FIG. Aa ′ in FIG.
It is a side view along a line.

As shown in FIGS. 1A and 1B, a single-layer ceramic 1 is used for the package for the purpose of reducing the package cost as in the conventional case. Reference numeral 2 denotes an alumina coat, and reference numerals 3, 5, and 7 denote external lead terminals of a source electrode, a gate electrode, and a drain electrode. Source electrode,
The internal metallized patterns 4, 6, and 8 of the gate electrode and the drain electrode are connected to the FET chip 15 by the bonding gold wire 10.

The internal metallized patterns 4 and 6 are connected to the external lead terminals 3 and 5 by the source side metallization 11 and the gate side metallization 16 shown in FIG. Here, the width of the gate side metallization 16 used in the present embodiment is the same width as the internal metallization pattern 6 of the gate electrode, and is provided so as to be smaller than the lead terminal width of the external gate electrode 5. . In addition,
The width of the gate side metallization 16 and the width of the internal metallization pattern 6 of the gate electrode do not necessarily have to be the same width. However, in consideration of the practical package dimensions and the required inductance, a pattern having a similar width is preferable. desirable.

Further, in this embodiment, the FET chip 15
As a high electron mobility transistor
ET (abbreviated as HEMT, HJ-FET, etc., but hereinafter referred to as HJ-FET) is used. Here, as the FET chip 15, AlGa of an HJ-FET having a gate length (Lg) of 0.25 μm and a gate width (Wg) of 200 μm is used.
FIG. 2 shows gain characteristics when an As / InGaAs-based chip is used. FIG. 2 shows the relationship between | S ₂₁ | ² obtained from the S-parameter measurement as the gain and the input inductance.

The input inductance is a fitting value obtained by simulation from the S parameter measured value when the pattern width of the gate internal metallized pattern 6 and the gate side metallized 16 is changed, and includes the inductance of the bonding gold wire 10. It is.
In this case, the input inductance uses a width of 0.5 mm as the external lead terminal width of the external gate electrode 5 and changes the pattern width of the internal metallized pattern 6 and the gate side metallized 16 of the gate electrode from 0.15 mm to 0.5 mm. Corresponds to the case where

As shown in FIG. 2, the FET chip 15
When the above-mentioned HJ-FET chip is used, there is an optimum value in the relationship between the input inductance and the gain, and the gain can be set to 10 dB. The gain of 10 dB can be improved by about 1 dB as compared with the conventional gain of about 9 dB. Therefore, it is shown that the gain characteristics can be improved by this embodiment.

Further, in order to obtain this improvement of 1 dB in gain by improving the chip characteristics, it is necessary to greatly reduce the gate length and the like, and there is a difficulty in manufacturing. However, in this embodiment, the input inductance value is reduced. Is determined not by the bonding gold wire 10 but by the metallization patterns 6 and 16 and is obviously obtained stably, which is advantageous in terms of low cost.

[0020]

As described above, according to the present invention,
The gain can be set to an optimum value by the input inductance including the internal metallization pattern of the gate electrode and the metallization pattern on the side surface of the package of the gate electrode, so that the gain characteristic can be improved as compared with the related art. In addition, since the input inductance is determined by the metallized pattern, the input inductance can be set stably, the gate length does not need to be significantly reduced, and the effects of the present invention can be achieved from the viewpoint of easy manufacturing and low cost. Notable.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a characteristic diagram of a gain and an input inductance of FIG.

FIG. 3 is a configuration diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ceramic package 2 Alumina coat 3 Source electrode external lead terminal 4 Source electrode internal metallization pattern 5 Gate electrode external lead terminal 6 Gate electrode internal metallization pattern 7 Drain electrode 8 Drain electrode internal metallization pattern 10 Bonding Gold wire 11 Source side metallization 15 Field effect transistor (FET) chip 16 Gate side metallization

Claims (3)

(57) [Claims] 1. A field effect transistor chip in a package is connected to a metallization pattern inside each package of a source electrode, a gate electrode and a drain electrode via a bonding line, and the metallization pattern inside each package corresponds to a source electrode. In a semiconductor device having a configuration in which each external lead terminal of a gate electrode and a drain electrode is connected to a package side metallization pattern, a package side metallization pattern of the gate electrode and an internal metallization pattern of the gate electrode are connected to an external lead terminal of the gate electrode. A semiconductor device formed to be narrower than a width. 2. The semiconductor device according to claim 1, wherein said package is a single-layer ceramic, and said field effect transistor chip is a heterojunction field effect transistor. 3. The semiconductor device according to claim 1, wherein the metallized pattern on the side surface of the package of the gate electrode has the same width as the internal metallized pattern of the gate electrode.