JPS6380354A - Data chain system - Google Patents

Abstract

PURPOSE:To reduce the time required for transfer processing by storing a memory address and the number of data transfers into a counter from a register and re-executing data transfer to apply data transfer between plural areas of the memory and data retransfer at the time of generating malfunction by one input/output operation it an error takes place during data transfer. CONSTITUTION:When a data transfer request signal 101 is detected, a data transfer control circuit 10 outputs a LOAD signal 103 to store a memory address from a FIFO register 1 in a counter 3 and to store a data transfer number from a FIFO register 5 in a counter 7. A memory address is given to a memory 9 from a counter 3 to start data transfer. In case of the output of a TC signal 105, the data transfer continues till no EXT signal 102 is detected. On the other hand, if an error takes place during data transfer, the memory address and the transfer number at that time are stored in the registers 4, 8, stored in the counters 3, 7 via selectors 2, 6 to re-execute data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data chain system for transferring data between multiple areas of memory.

(Conventional technology) Conventionally, when transferring data between multiple areas of memory,
The data transfer is completed once for each different area, and when the completion of the transfer is reported by a predetermined interrupt signal, the data transfer is started for the next area by specifying the mesori address and the number of data transfers again. This method was common.

Further, even if a malfunction occurs during data transfer, the data transfer is once terminated, predetermined interrupt processing is performed, and data transfer is re-executed from the memory address at which the malfunction occurred, as described above.

(Problem to be Solved by the Invention) In the conventional data chain method described above, whenever a memory area is different or a malfunction occurs during data transfer, an interrupt process is performed to end the transfer, and the memory address and Since it is necessary to issue a data transfer command specifying the number of transfers, processing time is required for this purpose, resulting in a problem that data transfer lacks speed.

The present invention has been developed to solve these problems, and is capable of transferring data between multiple areas of the system with -1 input/output operations. The purpose of the present invention is to provide a data chain method that can automatically re-execute data transfer even when data is transferred, and can significantly shorten data transfer processing time.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a first FIFO register that holds an initial value of a memory address, a first counter that counts memory addresses, and a first FIFO register that holds an initial value of a memory address. If a malfunction occurs, a first register holds the memory address at the time of the malfunction, and either the output of the first FIFO register or the output of the first register is used as the memory address to be stored in the first counter. A first selector for selection, a second FIFO register that holds the initial value of the number of data transfers, a second counter that counts the number of data transfers, and, if a malfunction occurs during data transfer, the data at the time of the malfunction. A second register that holds the number of data transfers; and a second selector that selects either the output of the second FIFO register or the output of the second register as the number of data transfers to be stored in the second counter. If the count value of the second counter reaches the stored number of transfers and the count value reaches the stored number of transfers, the initial value of the next memory address is stored from the first FIFO register to the first counter, and at the same time, the initial value of the next memory address is stored from the second FIFO register to the second The data transfer is continued by storing the initial value of the next data transfer count in the second counter. On the other hand, if a malfunction occurs during the data transfer, the data transfer is performed from the first register via the first selector. A configuration in which the memory address at the time of the malfunction is stored in one counter, and at the same time, the number of data transfers at the time of the malfunction is stored in the second counter from the second register via the second selector, and the data transfer is re-executed. It's Toshide.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a data transfer device using a data chain method according to this embodiment.

In the drawing, 1 indicates a first FIFO (First in First) that holds the initial value of the memory address.
out) register, 3 is a first counter that counts memory addresses, 4 is a first register that holds the memory address where the error occurs when an error is detected during data transfer, 2 is a first selector; As a memory address to be stored in the first counter 3 that counts memory addresses,
Either the output of the first FIFO register 1 or the output of the first register 4 is selected and output.

In addition, 5 is a second FI that holds the initial value of the number of data transfers.
FO register, T is the second counter that counts the number of data transfers, 8 is the m
The second register 6 is a second selector that holds the number of data transfers when b occurs, and the number of data transfers stored in the second counter 7 that counts the number of data transfers is as follows:
Either the output of the second FIFO register 5 or the output of the second register 8 is selected and output. Furthermore, 9 is a memory, and 10 is a data transfer control circuit.

From the second FIFO register 5, while holding the initial value of the number of data transfers, the EX
A T signal 102 is output. From the data transfer control circuit 10, a LOAD signal 103, a CNT signal 104, a SEL
A signal 108 is output to a predetermined block. The LOAD signal 103 is transmitted to the first counter 3 from the first FIFO register 1.
In addition to storing the initial value of the memory address from the first register 4 or the memory address at the time of error occurrence from the first register 4,
This is a control signal for storing in the second counter T the initial value of the number of data transfers from the second FIFO register 5 or the number of data transfers from the second register 8 when an error occurs.

The CNT signal 104 is a control signal for the first counter 3 and the second counter 7 to count the memory address and the number of data transfers.

A second counter 7 counts the number of data transfers.
When the count number reaches the stored number of data transfers,
A TC signal 105 is output from the second counter T to the data transfer control circuit 10.

On the other hand, the first selector 2 and the second selector 6 normally select the initial values of the memory addresses held in the first FIFO register 1 and the second FIFO register 5, but the data transfer control circuit 10 Save errors during transfer to memory 9.
When detected from the signal 106 from the register 106, the SEL signal 108 is input, and the output of the first register 4 and the output of the second register 8 are controlled to be selected and output. In addition,
The first register 4 and the second register 8 hold the memory address and the number of data transfers when an error during data transfer is detected from the signal 106 from the memory 9.

Now, if data is transferred from memory address A a number of times, from memory address B a number of times F, and from memory address C a number of times F,
First, initial values A, B, and C of memory addresses are stored in the first FIFO register 1, and initial values E and F of the number of data transfers are stored in the second FIFO register 5, respectively, based on a program. When the data transfer control circuit 10 detects the data transfer request signal 101, it outputs a LOAD signal 1.
03, stores the memory address A from the first FIFO register 1 into the first counter 3, and at the same time stores the memory address A from the first FIFO register 1 into the first counter 3.
Control is performed so that the number of data transfers is stored in the second counter T from the register 5.

Then, the memory address A is given from the first counter 3 to the memory 9, and data transfer starts. and,
Until the count number of the second counter 7 reaches the stored number of data transfers (that is, until the TC signal 105 is output), the CNT signal 104 is sent every - times of data transfer.
is output, and the memory address and the number of data transfers continue to be counted.

After that, when the TC signal 105 is output, the data transfer control circuit 10 detects the EXT signal 102, and the first FIF
The next memory address B from the O register 1 is stored in the first counter 3, and at the same time, the next data transfer count E from the second FIFO register 5 is stored in the second counter 7, and data transfer is continued.

Similarly, data transfer is performed continuously until the EXT signal 102 is no longer detected when the TC signal 105 is output, that is, until F data transfers from memory address C are completed. When the data transfer is completed, the data transfer control circuit 10 outputs the INT signal 107 to report the completion of the data transfer.

In addition, if an error occurs during data transfer, the memory address and the number of data transfers at that time are held in the first register 4 and second register 8, and the memory address and the number of data transfers are held in the first register 4 and the second register 8, The memory address and the number of data transfers at the time when the error occurred are stored in the second counter 7, and the data transfer is re-executed. If the data transfer is successful as a result of the re-execution, the data transfer will continue, but if an error is detected at the same memory address again as a result of the re-execution, the data transfer will be terminated at that point and the process will be restarted. N
The T signal 107 reports the end of the data transfer.

As described above, in this embodiment, as in the conventional technology, even if the memory areas are different or an error occurs during data transfer, the interrupt processing for the end of transfer, the specification of the memory address and the number of data transfers, and the data transfer It is possible to automatically continue data transfer with − times of input/output operations without processing commands or the like.

(Effects of the Invention) As explained above, the present invention allows data to be transferred between multiple areas of memory in - times of input/output operations, and to automatically transfer data even if an error occurs during data transfer. Since the data transfer is re-executed from the memory address where the error occurred, the processing time for data transfer can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data transfer device using a data chain method according to an embodiment of the present invention. 1... First FIFO register 2... First selector 3... First counter 4... First register 5... Second FIFO register 6... Second selector T... Second counter 8...Second register 9...Memory 10...Data transfer control circuit

Claims (1)

[Claims] a first FIFO register that holds initial values of memory addresses; a first counter that counts memory addresses;
When a malfunction occurs during data transfer, the first register holds the memory address at the time of the malfunction, and the first register stores the memory address stored in the first counter.
a first selector that selects either the output of the IFO register or the output of the first register; a second FIFO register that holds an initial value of the number of data transfers; and a second counter that counts the number of data transfers. , when a malfunction occurs during data transfer, a second register that holds the number of data transfers at the time of the malfunction, and an output of the second FIFO register or the second register as the number of data transfers to be stored in the second counter; a second selector for selecting one of the outputs of the second counter, and when the count value of the second counter reaches the stored number of transfers, the next memory is transferred from the first FIFO register to the first counter. At the same time as storing the initial value of the address, the second F
The data transfer is continued by storing the initial value of the next data transfer count from the IFO register to the second counter. On the other hand, if a malfunction occurs during data transfer, the data transfer is performed from the first register to the first selector. At the same time, the memory address at the time of the malfunction occurrence is stored in the first counter via the second register, and the number of data transfers at the time of the malfunction occurrence is stored in the second counter from the second register via the second selector, and the data is transferred. A data chain method that is characterized by re-executing.