JPS63191252A - Pipeline synchronizing system - Google Patents

Abstract

PURPOSE:To improve the performance of a processor by estimating the processing start time point of an optional asynchronous device having its working cycle time shorter than a pipeline and setting this estimated time point in response to the pipeline. CONSTITUTION:For a processor consisting of a CPU, a CHP, a main memory controlled by a pipeline, etc., the CPU and the CHP serving as the access sources to the main memory deliver requests in each cycle. Here the buffers 7-10 are provided to stack access requests. Then the number of cycles after which the accesses given from the CPU and the CHP are processed are estimated from the states of said buffers and the busy state of a key memory so that the synchronism is obtained. That is, an estimating circuit 13 is provided to estimate the processing start time point of an asynchronous device in case the working time of another asynchronous device which works in parallel with the pipeline is smaller than the working time of the pipeline. Then the estimated time point is linked with the pipeline. Thus the execution timing of another device can be easily identified from the pipeline.

Description

[Detailed Description of the Invention] [Summary] In a processing device consisting of a CPU, a CHP, a pipeline-controlled main storage device, etc., the CPU/CHP, etc., which is the source of access to the main storage device, issues a request every cycle. . However, the key storage device has a longer access time and operates asynchronously with each other. Therefore, in the present invention, a plurality of buffers are provided for stacking access requests, and the CPU /C
It is now possible to predict and synchronize the number of cycles after which accesses from HP will be processed.

[Industrial application field]

The present invention relates to a synchronization method between a pipeline and other asynchronous devices in a processing device operating in a pipeline.

If another device that performs processing in parallel with a pipeline is asynchronous and has a different operating cycle than that pipeline, it is necessary to synchronize the processing results of both. This paper relates to an efficient synchronization method for that purpose.

[Conventional technology]

FIG. 5 shows an example of a processing device for pipeline operation to which the present invention is applied.

In FIG. 5, 21 and 22 are respectively central processing unit C
PU, 23 is a channel processor CHP.

24 is a storage control device MCU, 25 is a key storage device KS,
26 is a main storage unit MSU.

Normally, the MSU access time is several tens of times longer than the CPU cycle time, so the MSU is controlled by a vibe line.

MSU is CPU-? 'When it receives an access request from the CHP, it sends an activation signal to the MSU, and at the same time sets necessary information such as the access address and store data in the IMSU pipeline.

When the pipeline processing of the MSU is completed, the MCU performs an error check and creates a response signal to the access source CPU or CHP.

The MCU has a KS for area protection and memory management of the MSU. KS includes a table of reference bits (R bits), change bits (C bits), etc.
The MCU accesses the KS and updates these bits to corresponding values each time the MSU is activated.

KS operates with a two-cycle access time.

On the other hand, since the access source CPU and CHP can issue an access request every cycle, the time from when the access request is accepted until the KS can be accessed depends on the number of access requests waiting to be executed. KS's busy (
BUSY) Varies depending on the situation. Furthermore, the MSU pipeline needs to be synchronized with the KS access processing in order to create a response signal at a constant timing.

In such a case, conventionally, the KS and MSU pipelines each execute processing asynchronously, identify the completion result of each processing, establish a link, and respond to the access source.

[Problem that the invention seeks to solve]

Conventional pipeline-operated processing devices require complex control and redundant control in order to synchronize processing results between pipelines operating in parallel and other asynchronous devices in relation to one processing request. A long operating cycle was required.

[Means for solving problems]

The present invention predicts the processing start point of an asynchronous device when the operation time of another asynchronous device that operates in parallel with the pipeline is shorter than the operation time of the pipeline, and transfers the prediction result to the pipeline. This allows the execution timing of other devices to be easily identified from the pipeline.

FIG. 1 shows, as an example, the fundamental configuration of the present invention applied to the conventional configuration shown in FIG.

In Figure 1.

1 is a main memory (MSU) pipeline.

2 is a key storage device KS.

3.4 are CPU ports that temporarily hold access request information (for example, address, store data, funxylan code) from different central processing units CPU.

5 is a CHP boat that temporarily holds access request information from the channel processor CHP.

6 is the CPU port 3, 4 . This is a selector SEL for selecting one port from CHP ports 5.

Buffers 1 to 10 sequentially stack access request information for the key storage device KS.

Reference numeral 11 denotes a selector SEL that sequentially selects one of the buffers 7 to 10 and supplies it to the key storage device KS.

12 is a key storage control circuit that manages the buffers 7 to 10 and controls access to the key storage device KS.

13 indicates the number of pieces of access request information stacked in the buffers 7 to 10 and the busy/busy status of the key storage device KS.
Based on the free status, each access request is sent to a key storage bag f
This is a prediction circuit that predicts the processing time in iKs.

Reference numeral 14 denotes a synchronization control circuit that links synchronization information indicating whether or not each access request is executed in the key storage device 2 to the MSU pipeline based on the predicted value predicted by the prediction circuit 13.

15 is an MSU activation signal.

16 is a response signal to the CPU/CHP of the access source.

Here, the access time of the MSU pipeline 1 is assumed to be several tens of cycles long, and the access time of the key storage device KS is assumed to be 2 cycles long5.
For example, it is assumed that the HP can issue an access request every cycle.

[Effect]

In Figure 1, when there is an access request from each CPU or CHP, the information of the access request (address, store data, funxylan code, etc.) is sent to the corresponding CP.
U port 3, 4. It is temporarily stored in CHP port 5.

The selector 5EL6 sequentially selects ports in which access request information is stored, sends an activation signal to the MSU, and sends necessary information to the MSU pipeline 1. This information is later used for error checking and when creating a response signal.

Each time the MSU is activated, the R bit and C bit in the key storage device 2 are updated. The access time to the key storage device 2 is 2 cycles long in this example, and on the other hand, access requests from the CPU, CHP, etc. are made in units of 1 cycle, so if an access request occurs every cycle, the length of the access request is 2 cycles. is required. Buffer or 10
enables this execution wait.

When the key storage control circuit 12 cannot immediately process the access request for which the MSU has been activated, the key storage control circuit 12 stores the information in the buffer 7.
10 to 10 in order, and each time the key storage bag M2 becomes empty, the selector 5ELII is used to select the oldest (longest waiting) buffer access request information, and based on that, < R/C Performs bit update processing.

FIG. 2 is a timing diagram showing an example of the control operation of the key storage $11111 circuit 12.

Figure 3 shows that access requests indicated by A, B, C, D, etc. are sent every cycle from the access source of the CPU or CHP.

Figures 1 to 2 show stack states of access requests in buffers 7 to 10.

Figure 3 shows the timing of the access request processing that the key storage device 2 accepts and accepts.

3 shows the execution period of the R/C bit update process of the key storage device 2. In FIG.

The prediction circuit 13 predicts the number of advance access requests waiting from buff to ten based on the access request that activated the MSU and the empty state of the key storage bag w2, as shown in FIG. Predict the time when the R/C bit update process for the access request will start as shown in FIG.

Create a predicted value.

The synchronization control circuit 14 associates this predicted value with the access request information proceeding through the MSU vibe line 1, and sets synchronization information indicating execution of update processing of the key storage device 2 when the predicted value time is reached. .

As a result, for each access request proceeding through the MSU pipeline 1, it becomes possible to identify the execution of the related update process in the key storage device 2 from the corresponding synchronization information, and generate a response signal to the access source. Timing can be easily determined.

〔Example〕

FIG. 3 shows an embodiment based on the basic configuration of the present invention shown in FIG.

In FIG. 3, 1 is an MSU pipeline, 12 is a key storage control circuit, 13 is a prediction circuit, 14 is a synchronization control circuit, 17 is a predicted value table, 18 is a predicted value register, 19
is a decoder, and 20 is a synchronization information register.

The synchronization control circuit 14 has a pipeline configuration corresponding to the MSU pipeline, and the predicted value register 18 configures each stage of the pipeline. The decoder 19 and the synchronization information register 20 are provided only in the second to eleventh stages of the pipeline (the decoder is not required in the eleventh stage).

The predicted value table 17 has a logical configuration as illustrated in FIG.
The number of waiting access requests in .

Depending on whether the key storage device 2 is busy or empty, the waiting time until the key storage device 2 becomes ready for processing is given as a predicted value (can be configured by a logic circuit).

The prediction circuit 13 receives an access request every time there is an access request.

Referring to the predicted value table 17 based on each state of the buffer and key storage device obtained from the key storage control circuit 12,
A corresponding predicted value is obtained and input to the synchronization control circuit 14.

The predicted value for each input access request is propagated through the predicted value register 18 of each stage in synchronization with the cycle progression of the access request in the MSU pipeline l, and is applied to the decoder 19 at the output of each stage. Ru.

The decoder 19 is configured to detect sequentially increasing predicted values according to the predicted values based on the predicted value table shown in FIG. For example, the second stage decoder is “00
10'', the third stage decoder responds to "0011", and the tenth stage decoder responds to "1010".

The output of each decoder 19 is the synchronization information register 2 of the same stage.
Input to 0.

With this configuration, the predicted value associated with a certain access request input to the synchronization control circuit is stored in the predicted value register 1 of each stage.
8 and reaches the stage corresponding to that value, that is, when the cycle time indicated by the predicted value has elapsed, the synchronization information detected by the decoder 19 of the relevant stage and set in the synchronization information register 20 is , and thereafter propagates to subsequent stages as the pipeline cycle progresses while responding to the access request.

(Effects of the Invention) According to the present invention, the processing start time of any other asynchronous device whose operation cycle time is shorter than that of the pipeline is predicted,
By adopting a simple method of associating the predicted value with the pipeline, synchronization can be achieved without reducing the processing speed as in the conventional method, and the performance of the processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a timing diagram showing an example of the control operation of the key storage control circuit in FIG. 1, and FIG.
The figure is a configuration diagram of one embodiment of the present invention. FIG. 4 is a configuration diagram of the predicted value table in FIG. 3. FIG. 5 is a block diagram of a conventional example of a processing device for pipeline operation to which the present invention is directed. In Figure 1. 1: MSU pipeline 2: Key storage devices 7 to 10: Buffer 12: Key storage control circuit 13: Prediction circuit 14: Synchronization control circuit

Claims (1)

[Claims] A pipeline (1) having an access source that makes an access request on a cycle-by-cycle basis and a relatively long operation cycle time that performs processing related to each access request, and a pipeline (1) that is shorter than this pipeline (1). In a processing device equipped with another asynchronous device (2) having an operation cycle time, a plurality of buffers (7 to 10) for temporarily stacking information of access requests sequentially input to the other device (2) are provided. , the plurality of buffers (7 to 1) into which the access request has been input.
According to the information on the advance access request stacked in 0) and whether the other device (2) is busy or free, predict the time at which the input access request will be processed in the other device (2). a prediction circuit (13), which associates the time predicted by the prediction circuit (13) with the operation cycle of the pipeline (1) and identifies the execution timing of related processing in another device (2) for each access request; A pipeline synchronization method characterized in that it is provided with a synchronization control circuit (14) that enables the synchronization.