JPH0533412B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a processing device consisting of a CPU, a CHP, a pipeline-controlled main storage device, etc., the CPU/CHP, etc., which is the source of access to the main storage device, issues a request every cycle. However, key storage devices have longer access times and operate asynchronously with each other, so in the present invention, multiple buffers are provided to stack access requests, and depending on the state of the buffers and the busy state of the key storage device, the CPU It is now possible to predict and synchronize the number of cycles after which accesses from CHP will be processed.

[Industrial application field]

The present invention relates to a synchronization method between a pipeline and other asynchronous devices in a processing device operating in a pipeline.

If another device that performs processing in parallel with a certain pipeline is asynchronous and has a different operating cycle from that of the pipeline, it is necessary to synchronize the processing results of both devices. The present invention relates to an efficient synchronization scheme for that purpose.

[Conventional technology]

FIG. 5 shows a simple example of a pipeline operation processing device to which the present invention is directed.

In FIG. 5, 21 and 22 are central processing units CPU, 23 is a channel processor CHP,
24 is a storage control unit MCU, 25 is a key storage device
KS, 26 is a main storage unit MSU.

Typically, the MSU access time is several tens of times longer than the CPU cycle time, so the MSU is controlled by a pipeline.

When the MSU receives an access request from the CPU or CHP, it sends a start signal to the MSU and at the same time sends necessary information such as the access address and store data.
Set in MSU pipeline.

When the MSU pipeline processing is finished, the MCU
performs an error check and checks the access source CPU and
Create a response signal to CHP.

MCU is used for MSU area protection and storage management.
Equipped with KS. The KS includes a table of reference bits (R bits), change bits (C bits), etc., and the MCU accesses the KS every time the MSU is activated and updates these bits to corresponding values.

KS operates with a two-cycle access time,
On the other hand, since the access source CPU and CHP can issue an access request every cycle, the time from receiving an access request to being able to access the KS depends on the number of access requests waiting to be executed and the number of KSs. Busy (BUSY) Varies depending on the situation. Additionally, since the MSU pipeline creates a response signal at a fixed timing, it needs to be synchronized with the KS access processing.

In such cases, conventional methods have been used in which the KS and MSU pipelines each execute processing asynchronously, identify the end result of each processing, establish a link, and respond to the access source.

[Problem that the invention seeks to solve]

Conventional pipeline-operated processing devices require complex control and redundant control in order to synchronize processing results between pipelines operating in parallel and other asynchronous devices in relation to one processing request. A long operating cycle was required.

[Means for solving problems]

The present invention predicts the processing start point of an asynchronous device when the operation time of another asynchronous device that operates in parallel with the pipeline is shorter than the operation time of the pipeline, and transfers the prediction result to the pipeline. This allows the execution timing of other devices to be easily identified from the pipeline.

Accordingly, the configuration of the present invention includes a memory device having a relatively long operation cycle time, an access source that accesses memory in units of clock cycles, and a pipeline that performs control processing for each access request for memory access. 1 and another device 2 having a shorter operating cycle time than the memory device that performs other accesses accompanying the memory access asynchronously with the pipeline 1. A plurality of buffers 7 to 1 that temporarily stack information on access requests to be made.
0, and the information on the stacked preceding access requests of the plurality of buffers 7 to 10 to which the access request has been input and the status of the other device 2 are busy or idle, the input access request is a prediction circuit 13 that predicts the processing time in another device 2; and a prediction circuit 13 that determines the stage of the access corresponding to the memory device being processed in the pipeline 1 from the time predicted by the prediction circuit 13, and This system is characterized by the provision of a synchronization control device that controls the completion reports of other devices 2 at the same time as the completion report timing.

FIG. 1 shows, as an example, the fundamental configuration of the present invention applied to the conventional configuration shown in FIG.

In Figure 1, 1 is a main memory (MSU) pipeline.

2 is a key storage device KS.

3 and 4 are CPU ports that temporarily hold access request information (for example, address, store data, function code) from different central processing units CPU.

5 is a CHP port that temporarily holds access request information from the channel processor CHP.

6 is a selector SEL for selecting one port from CPU ports 3 and 4 and CHP port 5.

7 to 10 are buffers for sequentially stacking access request information to the key storage device KS.

Reference numeral 11 denotes a selector SEL that sequentially selects one of the buffers 7 to 10 and supplies it to the key storage device KS.

12 is a key storage control circuit that manages the buffers 7 to 10 and controls access to the key storage device KS.

13 indicates the number of pieces of access request information stacked in buffers 7 to 10 and the key storage device.
A prediction circuit that predicts the time each access request will be processed in the key storage device KS based on the busy/free state of the KS.

Reference numeral 14 denotes a synchronization control circuit that links synchronization information indicating whether or not each access request is executed in the key storage device 2 to the MSU pipeline based on the predicted value predicted by the prediction circuit 13.

15 is an MSU activation signal.

16 is a response signal to the CPU/CHP of the access source.

Here, the access time of MSU pipeline 1 is assumed to be several tens of cycles long, and the key storage device
It is assumed that the access time of the KS is two cycles long, and that each CPU and CHP can issue an access request, for example, every cycle.

[Effect]

In Figure 1, when there is an access request from each CPU or CHP, the information of the access request (address, store data, function code, etc.) is temporarily stored in the corresponding CPU ports 3 and 4 and CHP port 5. Ru.

The selector SEL6 sequentially selects ports in which access request information is stored, sends an activation signal to the MSU, and sets necessary information in the MSU pipeline 1. This information will be used later when creating an error check and response signal.

Each time the MSU is activated, the R bit and C bit in the key storage device 2 are updated. In this example, the access time of key storage device 2 is 2
On the other hand, access requests from the CPU, CHP, etc. are made in units of cycles, so if an access request occurs every cycle, it will be necessary to wait for execution. Buffers 7 to 10 enable this execution waiting.

When the key storage control circuit 12 cannot immediately process the access request for starting the MSU, it sequentially stacks the information in buffers 7 to 10, and each time the key storage device 2 becomes empty, it stacks the information in the buffer using the selector SEL11. The access request information is selected from the oldest one (the one with the longest waiting time), and the R/C bit is updated based on it.

FIG. 2 is a timing diagram showing an example of the control operation of the key storage control circuit 12.

The diagram shows that from the CPU or CHP access source,
This indicates that access requests indicated by A, B, C, D, . . . are transmitted in every cycle.

The figure also shows the stack state of access requests in buffers 7 to 10.

The figure shows the timing of the access request process when the key storage device 2 accepts the process.

The figure shows the execution period of the R/C bit update process of the key storage device 2.

The prediction circuit 13 predicts the number of advance access requests waiting in the buffers 7 to 10 and the busy/empty state of the key storage device 2 based on the access request that activated the MSU, as shown in FIG. R/ of that access request as shown in
The time at which the C bit update process will start execution is predicted and a predicted value is created.

The synchronization control circuit 14 associates this predicted value with the access request information proceeding through the MSU pipeline 1, and sets synchronization information indicating execution of update processing of the key storage device 2 when the predicted value time is reached. .

As a result, for each access request proceeding through the MSU pipeline 1, it is possible to identify the execution of the related update process in the key storage device 2 from the corresponding synchronization information, and generate a response signal to the access source. Timing can be easily determined.

〔Example〕

FIG. 3 shows an embodiment based on the basic configuration of the present invention shown in FIG.

In Figure 3, 1 is the MSU pipeline, 1
2 is a key storage control circuit, 13 is a prediction circuit, 14 is a synchronization control circuit, 17 is a predicted value table, 18 is a predicted value register, 19 is a decoder, and 20 is a synchronization information register.

The synchronization control circuit 14 has a pipeline configuration corresponding to an MSU pipeline, and the predicted value register 18 configures each stage of the pipeline. Decoder 19 and synchronization information register 20
is provided only from the second stage to the 11th stage of the pipeline (the 11th stage does not require a decoder).

The predicted value table 17 has a logical configuration as illustrated in FIG. 4, and stores the number of waiting access requests in buffers 7 to 10 in FIG.
Depending on whether the key storage device 2 is busy or empty, the waiting time until the key storage device 2 becomes ready for processing is given as a predicted value (which can be configured by a logic circuit).

Every time there is an access request, the prediction circuit 13
Predicted value table 1 based on the buffer obtained from the key storage control circuit 12 and each state of the key storage device.
7, the corresponding predicted value is determined and inputted to the synchronization control circuit 14.

The predicted value for each access request entered is
The prediction value register 18 of each stage is propagated in synchronization with the cycle progress of the access request in the MSU pipeline 1, and the output of each stage is sent to the decoder 19.
is applied to

The decoder 19 is configured to detect sequentially increasing predicted values according to the predicted values based on the predicted value table shown in FIG. For example, the second
The decoder of the third stage responds to "0010", the decoder of the third stage responds to "0011", and the decoder of the tenth stage responds to "1010".

The output of each decoder 19 is input to the synchronization information register 20 at the same stage.

With this configuration, the predicted value associated with a certain access request input to the synchronization control circuit progresses through the predicted value register 18 of each stage, and when it reaches the stage corresponding to the value, that is, the predicted value indicates When the cycle time has elapsed, decoder 1 of the corresponding stage
The synchronization information detected by 9 and set in the synchronization information register 20 is thereafter propagated to subsequent stages as the pipeline cycle progresses, corresponding to the access request.

〔Effect of the invention〕

According to the present invention, by using a simple method of predicting the processing start time of any other asynchronous device whose operation cycle time is shorter than that of the pipeline and associating the predicted value with the pipeline, Thus, synchronization can be achieved without reducing the processing speed, and the performance of the processing device can be improved.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is a diagram showing the basic configuration of the present invention.
A timing diagram showing an example of the control operation of the key storage control circuit in the figure, FIG. 3 is a configuration diagram of one embodiment of the present invention,
FIG. 4 is a block diagram of the predicted value table in FIG. 3, and FIG. 5 is a block diagram of a conventional example of a pipeline operation processing device to which the present invention is applied. In FIG. 1, 1: MSU pipeline, 2: key storage device, 7 to 10: buffer, 12: key storage control circuit, 13: prediction circuit, 14: synchronization control circuit.

Claims (1)

[Scope of Claims] 1. A memory device with a relatively long operation cycle time, an access source that accesses memory in units of clock cycles, and a pipeline 1 that performs control processing for each access request for memory access. and another device 2 having a shorter operation cycle time than the memory device that performs other accesses accompanying the memory access asynchronously with the pipeline 1. Multiple buffers 7 to 1 that temporarily stack information on access requests
0, and the information on the stacked preceding access requests of the plurality of buffers 7 to 10 to which the access request has been input and the status of the other device 2 are busy or idle, the input access request is a prediction circuit 13 that predicts the processing time in another device 2; and a prediction circuit 13 that determines the stage of the access corresponding to the memory device being processed in the pipeline 1 from the time predicted by the prediction circuit 13, and determines the access stage of the memory device being processed in the pipeline 1. A pipeline synchronization method characterized in that a synchronization control device is provided for controlling the completion report of another device 2 to be performed at the same time as the completion report timing.