JPS6380292A - Display controller - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a display control technology and a technology that is particularly effective when applied to a display address output control method for an image memory. This invention relates to a technique that is effective for use in a display control device in a graphic display system used as a graphics display system.

[Prior Art] Conventionally, dual-port memories have been provided that are capable of outputting serial data at the same time as random access for data writing (for example, NEC Corporation).
Xm dual port memory μPD41264C, dual port memory HM53461 manufactured by Hitachi, Ltd.
and HM53462). This dual port memory.

Since it can output 256-bit serial data at a speed of 25 MHz, it is suitable for a frame buffer that stores image data for a CRT display device.

In the dual-port memory mentioned above, data for one row (256 bits) read from the memory cell array is output from the serial port one after another, and if left as is, the first data will be output again when the final data is output. That's where it gets done.

It is necessary to read data for the next row from the memory cell array in a timely manner in accordance with the output timing of the final data. However, when controlling a dual-port memory using a 1-display controller, it is very difficult to control the timing of outputting an address to the dual-port memory in accordance with the output timing of the final data and transferring data to the serial port. difficult.

Therefore, as shown in FIG. 4, the display controller LSI
A method has been proposed in which a control circuit 2 for controlling the timing of data transfer in a dual-port memory is connected to I (Nikkei McGraw-Hill, June 30, 1986).
(Refer to pages 238 to 241 of "Nikkei Electronics"), the external control circuit 2 is constituted by, for example, a gate array, and includes a preset circuit that generates a pseudo display address in order to detect the timing of data transfer. A counter 3 is provided. And this preset
Counter 3 is operated in synchronization with the serial address counter in the dual-port memory by clock SC.

[Problems to be Solved by the Invention] In the display control system as described above, a dual-port memory control circuit consisting of a gate array etc. is required separately from the display controller LSI, and a serial control circuit for the dual-port memory is required. If the port length is changed, the number of bits in the preset counter in the gate array must be changed. In addition, when operating the serial port of a dual-port memory with a clock frequency that is twice, four times, eight times, etc. the memory cycle of the display controller, the display address calculation section in the display controller and the gate +2. Both preset counters in the array. +4. It is necessary to perform inklinting in steps such as +8...

Furthermore, in the display control system, the drawing processing period within the display controller is controlled by a control signal called a wait signal WAIT between the display controller and the gate array. Therefore.

Considering the signal delay time between LSI chips, the WAIT signal is asserted for a longer period than necessary (3 memory cycles) to inhibit drawing, and the drawing efficiency is reduced accordingly.

In the display control system described as the conventional technology,
The present inventors have revealed that there are the above-mentioned problems.

An object of the present invention is to enable timely data transfer in a dual-port memory to be realized with a single display control device without providing an external control circuit.

It is another object of the present invention to change the serial port length of a dual-port memory, and to enable a dual-port memory to be operated at a clock speed of 2 times, 4 times, 8 times, etc. of the memory cycle. It is an object of the present invention to provide a display control device that can easily handle even such cases.

Still another object of the present invention is to provide a display control technique that does not inhibit drawing processing for an unnecessarily long period when outputting a display address to a dual-port memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a register for setting the display address output conditions in the display controller LSI, and a display address comparison section for successively comparing the conditions in the register and the display address calculated by the display address calculation section are provided, and the display The display address is outputted to the outside only when the display address calculated by the address calculation unit matches the conditions in the register.

[Operation] According to the above-described means, by supplying the dual-port memory with a clock having the same frequency as the clock supplied to the display control device or an integral multiple thereof, the serial address counter in the dual-port memory can be controlled. The address corresponding to the address can be obtained by the display address calculation unit, and as a result, the display address can be supplied to the dual-port memory at the desired timing, making it possible to do so without installing an external control circuit. The above object of being able to realize timely data transfer in a dual-port memory with one display control device can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a display controller LSI having a drawing function.

In this embodiment, although not particularly limited, a display control section including, for example, a microprogram type control section 11, a display address calculation section 2 that generates a display address for reading display data from the image memory, etc. is used in the image memory. A drawing process unit 20 is provided that calculates image data to be drawn and a drawing address indicating the drawing position thereof.

The display control unit is provided with a display address register 13 that holds the calculated display address and an address increment value register 14 that sets the update width of the address. , the display address is incremented by the update width in the address increment value register 14 and returned to the display address register 13 via the bus 15. In this way, the display address is constantly updated within the display control section.

Furthermore, the display control section is provided with a display address comparison section 16 and an output condition setting register 17 for setting the output conditions of the display address. When the display address matches the conditions set in the register 17, a match detection signal is output. As a method of setting conditions to the output condition setting register 17, for example, as shown in FIG.
A method is adopted in which the condition is satisfied when all bits of the display address corresponding to the bit set to "1" become "O".

On the other hand, the bus 15 and the drawing process unit 20 are connected to a multiplexer 18, and the display address calculated by the display control unit and the drawing address calculated by the drawing process unit can be output to the outside via the multiplexer 18. has been done. Among these, the display address is outputted to the outside by the multiplexer 18 only when a coincidence detection signal is output from the display address comparison section 16, and at this time writing of drawing data by the drawing process unit 20 is prohibited. There is.

Further, the coincidence detection signal outputted from the display address comparison section 16 is supplied to the status signal generation section 19 together with the drawing output signal outputted from the drawing process unit 20, and whether the address being output is related to display or drawing is determined. A status signal indicating the status is output to the outside.

In the display controller of the above embodiment, when the display address calculation unit 12 is operated with the clock CLK having the same frequency as the serial clock SC supplied to the image memory consisting of a dual-port memory, the address increment value is stored in the address increment value register 14. +1 is set, and the lower 7 bits of the output condition setting register 17 are set to "1" to operate. Then, the display address in the display address register 13 is operated by the display address calculation section 12 in the same manner as the serial address counter in the image memory. Therefore, when the column address, such as the lower 7 bits of the display address, becomes all "0", the upper 7 bits (row address) of the display address are output, and the display data is read out in a timely manner. Moreover, at that time, the status signal generator 1
Display data such as 256 bits read from the memory cell can be transferred to the serial port using the status signal output from the memory cell.

Note that the bit to be set to "1" in the output condition setting register 17 may be determined depending on the length of the serial port of one image memory, etc.

On the other hand, the frequency of the serial clock SC supplied to the image memory is equal to the operating clock CLK of the display controller LSI.
If the value is 2 times, 4 times, 8 times, etc., the increment value is +2. +4. Set a value like +8... Then, even if the clock frequencies are different, the display address is updated at the same speed as the value of the serial address counter in one image memory. At this time, among the lower 7 bits of the output condition setting register 17, the bits excluding the 1st bit, 2nd bit, 3rd bit, etc. from the least significant side are set to "1".
(Figure 2 (A) shows a state in which all but two bits are set to "1"), then the bits corresponding to the bits in the output condition setting register 17 where "1" is set are set. When all the bits of the display address become rOJ, the upper 7 bits of the display address are output as a row address, and read and transfer of the data of the next row in the image memory is executed in a timely manner.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, a display address calculation section and a comparison section are integrated, and the comparison with the setting conditions in the output condition setting register 17 is performed at the same time as the display address calculation ends. The other configuration is the first Q creeping type & fJ1! Instead of the output condition setting method for Mτ (see Figure 2 (A)), a mask register is provided in addition to one condition setting register as shown in Figure 2 (B), and the condition setting register has a comparison register. The address to be compared is set, and information for masking bits of the set comparison address that do not need to be compared is entered in the masking register.

In this way, the address output condition can be set to the point in time when the column address matches any set column address.

As explained above, in the above embodiment, there is a register in the display controller LSI that sets the display address output condition, and the conditions in the register are successively compared with the display address calculated by the display address calculation section. A display address comparison section is provided, and the display address calculated by the display address calculation section is outputted to the outside only when the display address calculated by the display address calculation section matches the conditions in the register. Serial address in image memory
Since there is no need to configure a circuit such as a preset counter that operates in the same way as a counter, timely control of the image memory can be performed using only the display controller LSI. In addition, the output conditions for one display address can be arbitrarily set using the output condition setting register, and even if the serial port length of the image memory differs, it can be easily handled by simply changing the register setting conditions. can.

There is also a register that sets the display address output conditions,
A display address comparison unit is provided to successively compare the condition in the register and the display address calculated by the display address calculation unit, and the display address calculated by the display address calculation unit matches the condition in the register. Since the display address is output externally only when the display address is output, the output cycle of the display address is reduced to one memory cycle due to the fact that there is almost no signal delay between the display address calculation section and the address comparison section. I was able to finish it,
This has the effect of shortening the period during which drawing processing is prohibited.

Furthermore, a register is provided for setting the update width of the address, and the display address calculated in the address calculation section is updated with an arbitrary update width according to the contents of this register. Even when setting the serial clock frequency to twice, four times, eight times, etc., the memory cycle of the display controller, the display address calculation section can be used without changing hardware such as an external preset counter. This can be resolved by changing the increment value of .

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, an explanation has been given of an application to a display controller LSI having a drawing process unit together with a display control section, but the present invention can also be applied to a display controller LSI consisting only of a display control section and other display control devices in general. can.

In the above explanation, the invention made by the present inventor was mainly applied to a display control device, which is the background field of application. An application can be considered in which an address set in a register is set as a system memory area that can (or cannot) be accessed, and when the address matches a condition register, the address is output (or output is prohibited). Also,
Applications such as outputting a flag or interrupt to notify an MPU or the like when an address enters an area where memory cycles are not possible can be considered.

Furthermore, it can be applied as a method of allocating internal memory to part of external memory addresses in LSIs and the like having internal memory.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, timely data transfer within the dual-port memory can be realized with one display control device without providing an external control circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a display controller LSI according to the present invention; FIGS. 2(A) and (B) are explanatory diagrams showing an example of a display address output condition setting method; FIG. FIG. 4 is a block diagram showing a second embodiment of the display controller LSI according to the present invention, and FIG. 4 is a block diagram showing a configuration example of a conventional display control system using dual-port memory. 1...Display control device (display controller LSI),
12...Display address calculation unit, 13...Display address register, 14...Address increment value register, 16...Display address comparison unit, 17...
...Output condition setting register.

Claims (1)

[Claims] 1. A display address calculation unit that forms a display address for reading image data from an external image memory, a register that sets output conditions for the display address, and conditions in the register and the above display. and a display address comparison section that sequentially compares the display address calculated by the address calculation section, and the display address is only when the display address calculated by the display address calculation section matches the condition set in the register. A display control device characterized in that the display control device is configured to output externally. 2. A signal generation circuit is provided which forms and outputs a status signal indicating that the display address is being outputted to the outside based on the coincidence detection signal from the address comparison section. The display control device according to scope 1. 3. A drawing processing unit that calculates image data to be stored in an external image memory and a drawing address indicating the drawing position of the image data, and based on the match detection signal from the display address comparison unit, Claim 1 or 2, characterized in that the output of the drawing address calculated by the drawing processing unit is prohibited.
The display control device described in Section 1. 4. A register is provided to set the address update width,
According to the contents of this register, the display address calculated in the display address calculation section is updated with an arbitrary update width. The display control device according to item 3.