JP2530826B2 - Display controller - Google Patents

Description

The present invention relates to a display control technique and a technique particularly effective when applied to a display address output control system for an image memory. For example, a dual port memory is used as an image memory. The present invention relates to a technique effectively used for a display control device in a graphic display system used as the above.

[Prior Art] Conventionally, a dual port memory capable of outputting serial data at the same time as random access for writing data has been provided (for example, a dual port memory μPD41264C manufactured by NEC Corporation [, Ltd.] Hitachi dual port memory HM53461 and HM534
62 etc.). The dual port memory, it is possible to output serial data of 256 bits at a rate of 25MH _Z, CRT
It is suitable for a frame buffer that stores image data of a display device.

In the above dual port memory, one row (256 bits) of data read from the memory cell array is output from the serial port one after another, and if left as it is, the first data is output again when the final data is output. Will be done. Therefore, it is necessary to read the data for the next one row from the memory cell array in a timely manner at the output timing of the final data. However, when controlling the dual port memory using the display controller, it is very difficult to control the timing of outputting the address to the dual port memory at the output timing of the final data and transferring the data to the serial port. .

Therefore, as shown in FIG. 4, the display controller LSI1
In addition, a method of connecting a control circuit 2 for controlling the timing of data transfer in the dual port memory has been proposed. (Published by Nikkei McGraw-Hill, June 30, 1986 issue,
See Nikkei Electronics, pages 238-241). The external control circuit 2 is composed of, for example, a gate array, and internally has a preset counter 3 for generating a pseudo display address for detecting the timing of data transfer. And this preset counter 3
However, the clock SC operates in synchronization with the serial address counter in the dual port memory.

[Problems to be Solved by the Invention] In the display control system as described above, a dual port memory control circuit including a gate array or the like is required separately from the display controller LSI, and the dual port memory serial When the port length is changed, it is necessary to change the number of bits of the preset counter in the gate array. Further, when operating the serial port of the dual port memory with a clock having a frequency of 2 times, 4 times, 8 times the memory cycle of the display controller, the display address operation unit in the display controller and the gate array It is necessary to make both of the preset counters of (3) increment by steps like +2, +4, +8 ....

Further, in the above display control system, the drawing processing period in the display controller is controlled by a control signal called a wait signal WAIT between the display controller and the gate array. Therefore, considering the signal delay time between LSI chips, a longer time than necessary (3 memory cycles)
The WAIT signal is asserted to prohibit drawing, and the drawing efficiency is reduced accordingly.

The present inventors have clarified that the display control system described as the prior art has the above problems.

An object of the present invention is to enable timely data transfer in a dual port memory with a single display control device without providing an external control circuit.

Another object of the present invention is when the serial port length of the dual port memory is changed or when the dual port memory is made to operate at a clock of 2 times, 4 times, 8 times the memory cycle. Also, it is to provide a display control device that can easily cope with the situation.

Still another object of the present invention is to provide a display control technique in which, when a display address is output to a dual port memory, drawing processing is not prohibited for a longer period than necessary.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, a register for setting the output condition of the display address in the display controller LSI and a display address comparison unit for sequentially comparing the condition in the register with the display address calculated by the display address calculation unit are provided, The display address is output to the outside only when the display address calculated by the address calculation unit matches the condition in the register.

[Operation] According to the above-mentioned means, by supplying the clock having the same frequency as the clock supplied to the display control device or the frequency which is an integral multiple thereof to the dual port memory, the serial address counter in the dual port memory The address corresponding to the address can be obtained by the display address calculation unit, and the display address is supplied to the dual port memory at a desired timing, so that the external address control circuit is not provided. The above object of enabling timely data transfer in a dual port memory with one display controller can be achieved.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a display controller LSI having a drawing function.

In this embodiment, although not particularly limited, for example, together with a display control unit including a microprogram control unit 11 and a display address calculation unit 12 that generates a display address for reading display data from the image memory, A drawing process unit 20 for calculating image data to be drawn and a drawing address indicating the drawing position is provided.

The display control unit is provided with a display address register 13 that holds the calculated display address and an address increment value register 14 that sets the update width of the address. The display address in the display address register 13 is displayed by the display address calculation unit 12. The display address is incremented by the update width in the address increment value register 14 via the bus 15
Returned to 13. In this way, the display address is constantly updated in the display control unit.

Further, in the display control unit, the display address comparison unit 16 and the output condition setting register for setting the output condition of the display address
17 is provided, the display address calculated by the display address calculation unit 12 is supplied to the display address comparison unit 16,
When the display address matches the condition set in the register 17, a match detection signal is output. As a method of setting conditions in the output condition setting register 17, for example, as shown in FIG. 2 (A), all the bits of the display address corresponding to the bit for which "1" is set in the output condition setting register 17 are all A method is adopted in which the condition is met when it becomes "0".

On the other hand, the bus 15 and the drawing process unit 20 are connected to the multiplexer 18, and the display address calculated by the display controller and the drawing address calculated by the drawing process unit can be output to the outside through the multiplexer 18. Has been done. Of these, the display address is output to the outside by the multiplexer 18 only when the match detection signal is output from the display address comparison unit 16, and at this time, writing of the drawing data by the drawing process unit 20 is prohibited. There is.

Further, the coincidence detection signal output from the display address comparison unit 16 is supplied to the status signal generation unit 19 together with the drawing output signal output from the drawing process unit 20, and the address being output is related to display or drawing. Is output to the outside.

In the display controller of the above embodiment, when the display address operation unit 12 is operated by the clock CLK having the same frequency as the serial clock SC supplied to the image memory including the dual port memory, the address increment value is stored in the address increment value register 14. +1 is set, and the lower 7 bits of the output condition setting register 17 are set to "1" to operate. Then, the display address in the display address register 13 is operated in the same manner as the serial address counter in the image memory by the display address calculation unit 12. Therefore, for example, the lower 7 bits of the display address
When all the column addresses such as bits become "0", the upper 7 bits (row address) of the display address are output, and the display data is read out in a timely manner.
Moreover, at that time, using the status signal output from the status signal generator 19, the display data such as 256 bits read from the memory cell can be transferred to the serial port. The bit for which “1” is set in the output condition setting register 17 may be determined according to the length of the serial port of the image memory.

On the other hand, the frequency of the serial clock SC supplied to the image memory is 2 times the operation clock CLK of the display controller LSI.
In the case of double, quadruple, octuple, etc., the address increment value register 14 is incremented by + 2, +
Set a value like 4, +8 ... Then, even if the clock frequencies are different, the display address is updated at the same speed as the value of the serial address counter in the image memory. In addition, at this time, "1" is set to the bits except the least significant one of the lower 7 bits of the output condition setting register 17 from the least significant side (1 bit, 2 bits, 3 bits, etc.). , "1" is set to all bits except 2). Then, when all the bits of the display address corresponding to the bit in which the "1" is set in the output condition setting register 17 become "0", the upper 7 bits of the display address are output as the row address and are stored in the image memory. The read transfer of the data of the next row is executed at a good timing.

A second embodiment of the invention is shown in FIG.
In this embodiment, the display address calculation unit and the comparison unit are integrated, and the comparison with the set condition in the output condition setting register 17 is performed at the same time when the display address calculation is completed. The other structure is the same as that of the first embodiment.

In addition, the output condition setting method (second
2B, instead of the condition setting register, a mask register is provided in addition to the condition setting register, and the address to be compared is set in the condition setting register, and the mask register is used. Contains information for masking bits that do not need to be compared among the set comparison addresses. By doing so, it becomes possible to set the address output condition at the time when the set arbitrary column address matches.

As described above, in the above embodiment, the register for setting the output condition of the display address in the display controller LSI and the condition in the register and the display address calculated by the display address calculation unit are sequentially compared. A display address comparison unit is provided, and the display address is output to the outside only when the display address calculated by the display address calculation unit matches the condition in the register. Serial address in memory
Since it is not necessary to configure a circuit such as a preset counter that operates in the same manner as the counter, the display controller LSI alone can timely control the image memory. Along with this, the output condition setting register
The output condition of the display address can be set arbitrarily,
Even if the length of the serial port of the image memory is different, it can be easily coped with by changing the setting condition of the register.

Further, a register for setting the output condition of the display adrel and a display address comparing unit for sequentially comparing the condition in the register with the display address calculated by the display address calculating unit are provided, and the display address calculating unit calculates Since the display address is output to the outside only when the displayed display address matches the condition in the above register, there is almost no signal delay between the display address calculation unit and the address comparison unit. As a result, the output cycle of the display address is completed in one memory cycle, and the period during which the drawing process is prohibited is shortened.

Further, a register for setting the update width of the address is provided, and the display address calculated in the address calculation unit is updated with an arbitrary update width according to the contents of this register. Even when the frequency of the serial clock is set to 2 times, 4 times, 8 times the memory cycle of the display controller, the increment in the display address calculation section without changing the hardware such as the external preset counter. It can be dealt with by changing the value.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the one applied to the display controller LSI having the drawing process unit together with the display controller has been described.
This invention is a display controller LS consisting of only a display controller.
I Others Applicable to general display control devices.

In the above description, the invention mainly made by the present inventor is described as being applied to a display control device which is a field of use which is the background of the invention, but the description is not limited to this, for example, in a coprocessor of MPU, etc. An application is conceivable in which the address set in the register is set as a system memory area where memory access is possible (or impossible), and the address is output (or output is prohibited) when the address matches the condition register. Also,
An application is also conceivable in which a flag or an interrupt output for notifying the MPU when the address enters the memory cycle impossible area is output.

Further, in an LSI having an internal memory, it can be applied as a method of allocating the internal memory to a part of the external memory address.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, one display control device can realize timely data transfer in the dual port memory without providing an external control circuit externally.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display controller LSI according to the present invention, FIGS. 2 (A) and 2 (B) are explanatory views showing an example of a display address output condition setting method, and FIG. A block diagram showing a second embodiment of a display controller LSI according to the present invention, and FIG. 4 is a block diagram showing a configuration example of a conventional display control system using a dual port memory. 1 ... Display control device (display controller LSI), 12 ...
Display address calculator, 13 ... Display address register, 14
...... Address increment value register, 16 ... Display address comparison unit, 17 ... Output condition setting register.

Claims (3)

(57) [Claims] 1. A display address calculation unit for forming a display address for reading image data from an external image memory, a first register for setting an output condition of the display address, and a condition in the first register. And an address comparison unit for sequentially comparing the display address calculated by the display address calculation unit with each other, and a second register for setting an address update width in the display address calculation unit. Accordingly, the display address calculated by the display address calculation unit can be updated with an arbitrary update width, and the display address calculated by the display address calculation unit matches the condition set in the first register. A display control device, characterized in that the display address is output to the outside only occasionally. 2. A signal forming circuit for forming and outputting a status signal indicating that a display address is output to the outside based on a match detection signal from the address comparing section. The display control device according to claim 1. 3. A drawing processing unit for calculating a drawing address indicating an image data to be stored in an external image memory and a drawing position of the image data, and based on a coincidence detection signal from the address comparing unit. The display control device according to claim 1 or 2, wherein the output of the drawing address calculated by the drawing processing unit is prohibited.