JPH04175662A - Digital storage oscilloscope - Google Patents

Abstract

PURPOSE:To provide a CPU with a long float by writing read-out information into a dual port RAM from which written information which is written not in synchronization with writing of the read-out information can be read out, and performing on the screen of a CRT tube a display indicating the information read out from the dual port RAM. CONSTITUTION:While processing for display operation is being carried out, read-out information which is the stored content of a dual port RAM 4 is read out in a fixed display cycle and character information stored in a character ROM 9 is read out by the information read out from the dual port RAM 4 and is converted into analogue signals by D/A convertors 10, 11 and a read-out display indicating the stored content of the dual port RAM 4 is performed on the screen of a CRT tube. In this case, transfer and writing of read-out information from a CPU to the dual port RAM 4 are possible irrespective of the read-out of the stored content from the dual port RAM 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital oscilloscope with a readout function, and more particularly to a digital storage oscilloscope that displays readout information of the oscilloscope as a vector on a CRT screen.

(Prior Art) Conventionally, when displaying a readout of a measurement range, etc. in a digital storage oscilloscope using an electrostatic deflection type CRT, for example, FIG. 6(a) or FIG. 6(b) is used.
).

In the conventional digital storage oscilloscope shown in FIG. 6(a), a character vector address is written in a character ROM 31, and characters to be displayed from the upper left corner of the CRT from the CPU to that position are stored in the character ROM 31. The upper address of the address is given to the character board 32 for each character as CPU calculation data, and in the same way, the CPU gives the X position data corresponding to the display position for each display character to the X position board 33 as CPU calculation data. The Y position data corresponding to the display position for each display character is supplied to the Y position port 34 as CPU calculation data.

On the other hand, the data from the character board 32 is supplied as the upper address of the character ROM 31, and the count output of the character dot counter 37 that counts the dot clocks (DOTCLK) is supplied as the lower address of the character ROM 31, so that data is sent from the character ROM 31 every dot clock. Read the vector address forming the character stored in the character ROM 31, and D/A the LSB side data of the vector address and the X position data.
The converter 35 performs analog conversion, the conversion output performs deflection in the X-axis direction, the D/A converter 36 converts the MSB side data of the vector address and the Y position data, and the conversion output performs the Y-axis deflection. Direction deflection is performed, one character is displayed, then the next character in the same row is displayed, all characters in the same row are displayed, and the Y position data is incremented to display the character in the next column. It was composed of

Further, in the conventional digital storage oscilloscope shown in FIG. 6(b), the data selector 42, address selector 43, and control selector 44 are (ROBUSY)→
At timing H, the address of the character ROM 46 in which data of the character to be displayed is stored is written into the lead-out RAM 41. Next, a pulse (RO9TART) is given every cycle T4, the R○ flip-flop 52 is preset, (ROBUSY) becomes L, and the data selector 42, address selector 43, and control selector 44 read out the readout RAM 41. side, and the address of the character ROM 46 stored at the address specified by the count value of the character data counter 45 is transferred to the lead-out data RAM 4.
It is read from 1.

The address of the character ROM 46 read out from the readout data RAM 41 is M of the character ROM 46.
The count value of the character dot counter 48 is given to the LSB side of the character ROM 46.
Dot clock (DOTCL) from character ROM46
Each dot data forming one character is output in synchronization with K).

The vector data field LSB side output from the character ROM 46 and the count value data of the X character position counter 47 are converted into analog by a D/A converter 50, and this analog conversion output is applied to the CRT as an X-axis deflection voltage. Further, the MSB side of the vector data output from the character ROM 46 and the count value data of the Y line counter 49 are converted into analog by a D/A converter 51, and this analog conversion output is applied to the CRT as a Y-axis deflection voltage. .

Therefore, each time the count value of the X character position counter 47 is incremented by 1, the displayed character position moves one character to the right on the CRT screen, and when all the characters at the same time are finished being displayed, the count value of the Y line counter 49 is incremented by 1. The characters will be displayed on the next line. As the Y line counter 49 overflows, (ROBUSY) becomes H, and the selectors 42 to 44 are switched to the CPU side again.

(Problem to be Solved by the Invention) However, in the conventional digital storage oscilloscope shown in FIG. 6(a), when the display period is T4, the calculation data from the CPU is as shown in FIG. 7(a). The period T, which is obtained by subtracting the transfer time T, from the display cycle T4, is C.
There is a margin for the PU, and during this period T, the CPU
can perform other tasks.

However, since period T is long and period T3 is short, CP
There is a problem in that the period during which U can perform other tasks becomes shorter.

In addition, in the digital storage oscilloscope shown in FIG. 6(b), the period T, as shown in FIG. 7(b),
The period T, which is obtained by subtracting the data transfer period T1 from the PU, is the spare period of the CPU, and the period T2 is a waiting period until the next transfer period, but during (ROBUSY)→H, the character ROM cannot be accessed and the high speed There was a problem that it could not be displayed.

By using dual port RAM, the present invention
It is an object of the present invention to provide a digital storage oscilloscope that can give a long margin to a CPU, display at high speed, and solve the above problems.

(Means for Solving the Problems) A digital storage oscilloscope of the present invention is a digital storage oscilloscope equipped with a readout function, and includes a dual port RAM that can read readout information written asynchronously with writing of the readout information. The device is characterized in that lead-out information is written in the dual-port RAM, and a display accompanying the read-out information read from the dual-port RAM is performed on the CR and T tube surfaces.

(Function) According to the digital storage oscilloscope of the present invention configured as described above, a dual port RAM is provided that can read readout information written asynchronously with writing of the readout information, and the readout information is read out from the dual port RAM. The readout information that has been written to the readout information is read out asynchronously with the writing of the leadout information, and the display accompanying the readout information is displayed on the CR and T tube surfaces, so the readout information can be read at high speed. Moreover, display with a high degree of freedom can be realized with less burden on the CPU.

(Example) The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In Figure 1, 1 is the data bus of the CPU, 2 is the CPU
3 indicates an address bus, and 3 indicates a readout control bus from the CPU.

4 is a dual port RAM in which readout information can be written and read out asynchronously with writing; the readout information is sent to the dual port RAM 4 via the data bus 1, and is sent to the dual port RAM 4 via the address bus 2.
It is stored in the address of dual port RAM 4 sent to 4.

A readout pulse generator 5 receives a readout start pulse sent via the readout control bus 3 and sends out a pulse (RSTA) synchronized with the readout start pulse during the readout period.

6 is a character dot counter that generates an address for reading the character bone vector data stored in the character ROM 9, and is connected to the readout control bus 3.
The output of the AND gate 6, which receives the dot clock (DOTCLK) and pulse (R8TA) sent from the clock, is counted as the clock (CLK), and the output of the count is supplied as the LSB side address of the character ROM 9 to perform an address bus. . Character dot counter -6
The character dot counter 6 is reset by the output of the OR gate 6, which receives the overflow output of the character ROM 9 and the MSB output of the character ROM 9, and the dot clock (DOT
CLK), the character dot counter 6 starts counting operation.

7 is a character data counter that counts the output from the NOR gate 6 via the inverter 7I as a clock (CADCLK) to generate a dual port RAM address for each character, and starts counting at the rising edge of the pulse (R5TA). The idea is to let them do this.

8 is an X character position counter that counts the clock (CADCLK) and generates the character position of the X axis on the CRT for each character, and receives the overflow output of the X character position counter 8 and the pulse (R3TA) as input. The output pulse of the OR gate 81 (RS T L
) to reset the X character position counter 8.

9 is the vector address of the X component of the display character.
On the B side, a character RO for generating a character vector address that generates the vector address of the Y component on the MSB side.
M, 10 is a D/A converter that receives the output of the character ROM 9 and the count value of the X character position counter 8 and converts it into an X-axis analog output; 11 is a character RO;
A D/A converter receives the output of M9 and the counted value of the Y line counter (row counter) 9 and converts it into a Y-axis analog output. 12 amplifies the output of the D/A converter 10 to change the driving voltage of the CRT. Generating X-axis direction drive amplifier, 15 is D/A
A Y-axis direction drive amplifier that amplifies the output of the converter 11 to generate a CRT drive voltage, 18 is a CRT drive voltage output terminal, 21 is a setting device when starting the Y line from the middle, 22 is a setting device It is preset with the output from 21,
This is a Y line counter that counts pulses (R8TL) inverted by the inverter 22. Y line counter 22
is set to be reset by the overflow output of the Y line counter 22 and the output of the OR gate 222 which receives the pulse (RSTA, ) as input.

The operation of this embodiment configured as described above will be explained.

As shown in FIG. 2, when the program is executed, display clear data for all data is sent from the CPU to the primary side of the dual port RAM 4 via the CPU data bus (step S1), and then the display screen data is is calculated and transferred to the dual port RAM 4 (step S2).

Steps 81 to S2 are display operation processing. Following step S2, oscilloscope processing is performed (
Step ), it is checked whether there has been a change in the readout display content, such as whether a display change has occurred due to a switch input or the progress of measurement content (step S6), and when it is determined that there is no change in the display content. Step S4 is executed. When it is determined in step S6 that there is a change in the lead-out display content, new display data is calculated following step S6 (step S8), and step S2 is executed following step S6. Here, step S is the oscilloscope operation,
Step S is display operation processing.

Even when the above-mentioned display operation processing is being performed, the readout information that is the storage content of the dual port RAM 4 is read out at a constant cycle of the display cycle T4 as shown in FIG. Character information stored in the character ROM 9 is read out based on the readout information read out from the character ROM 9, and the read character information is converted into an analog signal by the D/A converter 10.11 and stored in the dual port RAM 4. A readout display accompanying the content is displayed on the CRT screen. In this case, it is possible to transfer and write lead-out information from the CPU to the dual-port RAM 4 regardless of reading the memory contents from the dual-port RAM 4, and if there is a change in the lead-out information as shown in FIG. 3(b), During the period T1, T, ', T, // other than the period T1, T, ', T, // during which the lead-out information is transferred due to the change, that is, the period when no transfer is performed, the CPU can perform other processing, This will free up the CPU.

As a result, the load on the CPU is reduced even if the CPU has a slow processing speed.

Next, lead-out display will be explained. Lead-out information transferred from the CPU data bus 1 is stored at an address of the dual port RAM 4 corresponding to the address data from the CPU address bus 2. A pulse (RSTA) from the readout pulse generator that receives the readout start pulse from the readout control bus 3.
) Character data counter 7 starts counting by
Address data for one character is output from. Character data counter 7 corresponds to each lead-out period (T4)
Be sure to start from zero, that is, at the top left of the CRT screen. The readout information stored in the dual port RAM 4 is read from the address specified by the address data output from the character data counter 7.

The readout information read out from the dual port RAM 4 is supplied to the character ROM 9 as MSB side data, and the clocks CC, LK from the AND gate 6□ are supplied to the character ROM 9 as MSB side data.
is counted by a character dot counter 6 to generate each dot address of one character.The count output is supplied to the character ROM 9 as LSB side data, and data corresponding to the lead-out information is read from the character ROM 9.

The character dot counter 6 receives a clock (D.

The count output of the character dot counter 6 is incremented by one address by one address (TCLK).
The character ROM 9 successively outputs data of dots forming each character as character dot data. The LSB side bits of the data read from the character ROM 9 and the count output of the X character position counter 8 are supplied to the D/A converter 10, converted into analog signals, and amplified by the X-axis direction drive amplifier 12. , is applied to the X-axis deflection plate of the CRT.

MS of data read from character R, OM 9
The number of bits on the B side and the count output of the Y line counter 22 are D
The signal is supplied to the /A converter 11, converted into an analog signal, amplified by the Y-axis drive amplifier 15, and applied to the Y-axis deflection plate of the CRT. By this application, characters corresponding to the lead-out information are displayed on the CRT tube surface. The position of this display is the X-axis position according to the count value of the X character position counter 8, and the Y-axis position according to the count value of the Y line counter 22.

The end of each dot occurs when the MSB of the data read from the character ROM 9 is zero, and when the MSB is zero, the character dot counter 6 is reset, the character data counter 7 is incremented by 1, and the data in the dual port RAM 4 is The data of the second character is accessed. Thereafter, digits 3 to N are displayed in the same way, and Y at N+1.
The line counter 22 is incremented by 1, and the next line is displayed in the same manner. When the previous line is displayed, the Y line counter 22 is reset and the next lead-out screen is displayed.

Here, the lead-out display will be specifically explained.

The readout information stored in the dual port RAM 4 is address data of the character ROM 9. An example will be explained in which the number II 2 n is displayed at the beginning of the position X at the top of the lead-out display on the CRT screen shown in FIG. 4. Assuming that the data for the number II 2 is stored at addresses 200 to 20F of the character ROM 9 as shown in FIG. 5(a), the MSB side data 20 indicating the address 200 is stored in the dual port RAM 4. has been done. Moreover, the display is as shown in FIG. 5(b) in contrast to FIG. 5(a).

Each dot address of each character is generated by the count value of the character dot counter 6 which counts the clock (CLK) output from the AND gate 6, and the clock (CLK) is generated.
CLK), the character RO is
The LSB side address of M9 is specified, and the dual port R
MSB of character ROM9 by output from AM4
When the side address is specified, the character ROM 9 synthesizes the address data output from the dual port RAM 4 and the address data specified by the count value of the character dot counter, and the character ROM 9 specifies addresses from 200 to 20F. Therefore, data 80, C6, C5, C4, . . . from character ROM 9
EE%F5 and F4.73 are read.

Several bits on the LSB side of the data read from the character ROM 9, in the above example, 3 bits are the LSB of the data on the X side.
As side data, the count value of the X character position counter 8 that counts the clock (CADCLK) is supplied to the D/A converter 10 as MSB side data of the X side data and converted into an analog signal. Also, the character RO
The MSB side number bits of the data read from M9, 4 bits in the above example, are used as the LSB side data of the Y image data by the Y line counter 22 that counts the clock (CLK).
The count value is supplied to the D/A converter 11 as MSB side data of the Y image data and converted into an analog signal. Therefore, by the output from the D/A converter 10, the x8
〃2/l is displayed at the position, and 7/2 at the X8 position
When n is finished displaying, X position counter 8
The count value is incremented by 1, and the following display is similarly made at the x2 position. When the display of X2 . . . Similar displays are made below.

In the above embodiment, the dual port R and AM4 are given the start address of the character ROM 9 to be displayed on the CRT screen, but instead of the start address, the CRT display data itself to be displayed on the CRT is transferred to the dual port RAM 4. It can also be displayed graphically by inputting it to . Therefore, dual port RAM
By simply setting the data on the primary side of 4, characters and graphics can be displayed from the secondary side in synchronization with this data.

(Effects of the Invention) As explained above, according to the present invention, in a digital storage oscilloscope equipped with a readout function,
Dual port RAM that can read readout information written asynchronously with writing leadout information
The readout information is written to the dual port RAM and the display accompanying the readout information read from the dual port RAM is displayed on the CRT screen. is read out, and a display accompanying the read out information is displayed on the CRT screen, which has the effect of realizing high-speed and highly flexible display with less burden on the CPU. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flowchart for explaining the operation of one embodiment of the present invention. FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 4 is an explanatory diagram of a lead-out display position according to an embodiment of the present invention. FIG. 5 is an explanatory diagram showing an example of storage contents of a character ROM according to an embodiment of the present invention and a display corresponding to the storage contents. FIGS. 6(a) and 6(b) are block diagrams of a conventional example. FIGS. 7(a) and 7(b) are explanatory diagrams showing the operation of the conventional example. 1...Data bus, 2...Address bus, 3...
Readout control bus, 4...Dual port RAM, 5...Readout pulse generator, 6...
・Character dot counter, 7...Character counter, 8...X character position counter, 9.
...Character ROM, 10 and 11...D/A converter, 12 and 15...X-axis direction amplifier and Y-axis direction amplifier, 22...Y line counter.

Claims (1)

[Claims] A digital storage oscilloscope with a readout function is equipped with a dual port RAM that can read readout information that has been written asynchronously with the writing of readout information, and writes readout information to the dual port RAM and reads it from the dual port RAM. A digital storage oscilloscope characterized by displaying readout information on a CRT screen.