JPH06103433B2 - Image display device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an image display device.

(Prior Art) Conventionally, this main image display device is as shown in FIG. 1, and the display position set in the coordinate address register 1 is compared with the output of the scan counter 3 driven by the timing generator 4. The match is detected by the match detection circuit 2, a display request signal is generated, and the display control circuit 5 is activated.
The character address is sequentially fetched from RAM6, the ROM7 which stores the display pattern together with the line address outputted from the display control circuit 5 is driven, the display information is fetched from the ROM7 as parallel data, and the shift register 8
In addition, the shift register 8 converts the data into serial data, shifts the shift register 8 with the column shift clock from the display control circuit 5, and supplies the shift register 8 as a video signal to the CRT 9.

FIG. 2 shows the relationship between the output of the ROM 7 and the display by using matrix dots of 5 rows × 8 columns. FIG. 2A shows the matrix dot pattern, and FIG. 2B shows the columns. The shift clock, (C) of the figure, shows the video signal of the second line address. That is, the line address is "2"
At that time, (10001) is output as parallel data from the ROM 7 and then fetched in the shift register 8 for serial conversion by the column shift clock.

As described above, the character address is read from the RAM6 for each display request signal and the ROM7 is directly operated.
Since the character address is written to RAM6 asynchronously from the outside of the device, the display flickers when the data of RAM6 is changed while operating ROM7 with the line address output from the display control circuit 5. was there.

(Object of the Invention) The object of the present invention is The purpose of this is to obtain an image display device in which display flicker is eliminated by a simple circuit.

(Structure of the Invention) According to the present invention, a display control circuit that outputs a read address and a line address based on a display request signal and a read address from the display control circuit are used for operation.
RAM, ROM operated by address information from RAM and line address from display control circuit, shift register for converting display information output from ROM into serial data, and display element for displaying output of shift register When writing the character code from the outside of the device to the RAM, based on a signal generated on an invalid display screen indicating a timing other than the valid screen and a write timing signal, within the timing of the invalid display screen area, And a write control circuit for outputting a write signal from the outside of the device.

(Example) Below, a specific example is given and demonstrated.

FIG. 3 shows an embodiment of the present invention. The ROM 17 is operated by the character address output from the RAM 16 for storing the character address written from the outside of the device and the line address output from the display control circuit 15 to output the character pattern to the shift register 18. This shift register 18 reads the character pattern output from ROM 17 in line dot units,
It is converted into serial data and driven by the column shift clock from the display control circuit 15, and the output as serial data is supplied to the CRT 19 as a video signal. Coordinate address register 1
By the character display request signal obtained by detecting the match between the output from 1 and the output from the scan counter 13 driven by the timing generator 14, the display control circuit 15 causes the RAM 16 to read the address for reading. , The character address is taken out from this RAM16, another line address is generated, the ROM17 is operated by these character address and line address, and the pattern data of the display character is output from the ROM17 in line dot units. . Here, the coordinate address register 11 stores the display start position. A timing signal ₂ and a signal ₁ generated in the invalid display screen area are applied to the write control circuit 20 from the timing generator 14 and the scan counter 13. The write control circuit 20 controls the time when the character address asynchronously input from the outside of the device is written in the RAM 16, and the write signal is generated in the invalid display screen area ( ₁ ) detected by the scan counter 13. .

A write control circuit 20 according to the present invention is shown in FIG.
A timing chart showing the operation is shown in the figure.

The write control circuit 20 has a latch 21, and is supplied to a write strobe latch 21 from the outside which is asynchronously input. In this embodiment, the write strobe is a low level signal as shown in FIG. 5, and the output of the latch 21 is inverted to the high level as shown in FIG. Supplied. On the other hand, since the clock 1 generated from the scan counter 13 in the invalid display screen area is supplied to the inversion clock terminal of the flip-flop 22, this flip-flop 22 causes the flip-flop 22 to rise to the high level of the latch 21. The level is stored, and its output becomes high level as shown in FIG. This high level output is a differentiation circuit
Supplied to 23.

At this time, since the inverted output of the flip-flop in the differentiating circuit 23 is at the high level, the data write signal W goes high as shown in FIG. 5 in synchronization with the change of the output of the flip-flop 22 to the high level. Invert to level.

When the clock 2 is generated from the timing generator 14, the flip-flop in the differentiating circuit 23 captures the high-level output of the flip-flop 22, so that the data write signal W is reset to the low level in synchronization with the clock 2. The signal W is supplied to the RAM 16 as a data write signal. Furthermore, at this time,
The output of the NAND gate 24 becomes low level by the clock 2 as shown in FIG. 5, and as a result, the latch 21 is reset to low level.

As is apparent from the above description, according to the present invention, even if the character address is written from outside the device while the character is displayed on the screen, the RAM is displayed at a place other than the effective display screen.
Since the writing signal of is generated, the problem of "flickering" disappears even if the displayed character is changed. It is also possible to make another storage circuit easy and write it again to the RAM every time the character code is input to the device, but this is not a good idea because the storage circuit and the interface circuit when writing to the RAM become complicated. Therefore, according to the present invention, the effect can be said to be great because it can be realized with a simpler circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional image display device.
2 (A), (B) and (C) are timing charts for explaining the display operation of the conventional image display device. FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a circuit diagram showing a specific example of the write control circuit of FIG. FIG. 5 is a timing chart for explaining the operation of FIG. 1,11 …… Coordinate address register, 2,12 …… Match detection circuit, 3,13 …… Scan counter, 4,14 …… Timing generator, 5,15 …… Display control circuit, 6,16 …… RAM,
7,17 …… ROM, 8,18 …… Shift register, 9,19 …… CR
T, 20 ... Write control circuit, 21 ... RS latch, 22
...... Flip-flop, 23 …… differential circuit, 24 …… NAND
Gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-50-82939 (JP, A) JP-A-56-51781 (JP, A) JP-A-57-155584 (JP, A) JP-A-58- 169628 (JP, A) JP-B 50-18731 (JP, B2) JP-B 50-23769 (JP, B2)

Claims (1)

[Claims] 1. A RAM for storing a character code indicating a character to be displayed on a display device, a ROM for storing character pattern data, and a display control circuit for outputting a read address of the RAM and a line address of the ROM. And a coordinate address register that stores a coordinate address indicating where on the screen the character is displayed,
It has a scan counter that operates at a predetermined clock, a match detection circuit that outputs a display request signal when the coordinate address and the contents of the scan counter match, and a shift register that converts the output of the ROM into serial data. ,
In response to the display request signal, the display control circuit outputs the read address of the RAM and the line address of the ROM, and the RO based on the character code and the line address obtained from the RAM at the read address.
The character pattern data from M is output as parallel data in line dot units corresponding to the line address,
An image display device for converting the parallel data to serial data in the shift register and displaying the serial data on the display device, wherein the character code to the RAM is generated asynchronously with the reading of the character code from the RAM. A write control circuit for responding to a write request is provided, and the scan counter is configured to generate a timing signal indicating an area other than the display effective area of the screen of the display device, and the write control circuit is configured to output the timing signal. An image display device that holds the write request until it is generated and writes a character code to the RAM based on the generation of the timing signal.