JPS59212883A - Crt display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention Technical Field The present invention relates to a CR suitable for use as one of the output devices of office computers, personal computers, word processors, and other computer application systems.
This CR is related to T-display control equipment, and in particular allows CRT displays that require high resolution, such as bitmap displays, to be sufficiently obtained using a video amplifier with conventional response characteristics.
The present invention relates to a T display control device.

2. Description of the Related Art In general, office computers, personal computers, and other computer application systems are connected to CRT display devices for data input/output operations.

In such a CRT display device, 1%CRT
There has been a problem in that display with a desired resolution cannot be obtained due to the influence of the operating characteristics of the video amplifier built into the display unit.

To facilitate understanding, a CRT display device will be briefly explained.

FIG. 7 shows a part of a CRT display control device conventionally used in computer application systems. FIG. 2 is a functional block diagram showing an example of the configuration. In FIG. 1r11, / is a CRT controller, ko is a display memory such as RAM that stores display data, 3 is a shift register that converts display data from parallel to serial, da is an address decoder, and shi is a CRT display unit. 6 is an AND gate circuit, and 7 is a system bus. Also %A
ゎ is a memory address given from the address bus of the system bus 7, C8 is a decode output signal of the address decoder, l0WR is a write command given from the control bus of the Toga System Bus, and l0RD is a read command given from the control bus as well. Command, D.A.
TA is data given from the data bus of system bus 7, WE, RAS, and CAS are memory control signals, VDAT
A is display data, LD is a load signal to the shift register 3, 5CLK is a shift clock, DE is a display enable signal that controls the antogenide circuit 6, H8YN
C is the horizontal synchronization signal, VSYNC is the vertical synchronization signal (No. 4, V
IDEO indicates Video No. 46.

The CRT display control device shown in FIG. 1 is connected via a system bus 7 to a micro CPU (not shown), an internal memory, an external memory such as a floppy disk, a keyboard, a blinker, a character pattern memory, etc. Each of these parts is controlled by.

Furthermore, although this figure shows the case of a CRT display control device that performs bitmap display, in the case of a character display: ttlJ control device, the memory co which stores display data and the shift register 3 are connected. The basic configuration is the same as that of the device shown in Figure 1, with the only difference being that a character generator is added in between, and dot pattern data is selected from the character generator based on the character code from the memory code and input to the shift register 3. It is similar to

The function of the CRT controller is, first, to write or read data into the display memory IJ 2 using the address An, data DATA, and write command 10WR or read command 10RD given from the system bus 7. Second, for display purposes, it operates to generate memory control j signals WE, RAS, and CAS in synchronization with a synchronization signal, and to sequentially generate addresses for reading data from the memory controller. Third, an operation is performed to generate a horizontal synchronizing signal H8YNC and a vertical synchronizing signal VSYNC for scanning the CRT display unit 5.

When performing CRT display, via the system busk,
Display start address and horizontal synchronization signal H8YNC1 vertical synchronization I of this CRT controller/hemorico V S
'CRT display unit S such as YNC? I
Parameters necessary for tlJ hai are set.

After that, the CRT controller sequentially reads out the data stored in the display memories 1 and 2 starting from the designated display start address.

The read display data VDATA is loaded in parallel into the shift register 3 by the load signal LD, and serially input bit by bit to the AND gate circuit 6 by the shift clock 5CLK.

AND gate circuit B uses this serial data and CRT
A video signal VIDEO is generated under an AND condition with a display enable signal DE given from the controller, and sent to the CRT display unit.

The CRT display unit 3 receives this video signal VI.
DEO, the horizontal synchronizing signal H8YNC1 and the vertical synchronizing signal VSYNC given from the CRT controller/ are used to display the data on the CRT screen.

When writing data to the display memory λ, a write command 10WR and data DATA are given to the CRT controller via the system bus 7, and an address An to the master address decoder is given. When reading data to the system bus 7 side, 1, transfer command l0RD
and address An are given.

By the way, high-resolution CRTs such as bitmap displays
In the case of display, the control device itself can relatively easily meet the requirements, or there is a limit to the resolution due to the operating characteristics of the video amplifier provided in the CRT display unit s shown in FIG. .

FIG. 2 is a block diagram showing a detailed configuration example of the shift register 3 shown in FIG. Reference numerals in the drawings are the same as in FIG. 1.

This shift register 3 has a 1m bit configuration, and has a load (c
'n1 bit display data VDATA by LD No.
or loaded in parallel. And shift clock 5
Display data driven by CLK and serially converted is generated from the output terminal QITl as a video signal VIDEO.

This video signal VIDEO is sent to a video amplifier provided in the CRT display unit s shown in FIG.

FIG. 3 is a time chart showing the correspondence between a conventional video input signal applied to a video amplifier in a CRT display unit and its output signal. In the drawings, t indicates the dot display time, t indicates the fall time of the video amplifier, tr indicates the rise time, and td indicates the actual light emission time of the phosphor dot.

In FIG. 3, the video signal VIDEO provided from the CRT display control device is shown in an ideal waveform so that the mutual relationship between input and output signals is clear.

On the CRT screen, bright dots are displayed when (7) VIDEO is at L level, and when it is at H level,
It is considered a non-door point. Note that the VIDEO in Figure 3 is N
This is the case of the RZ (non-return-to-zero) method.

Furthermore, the shift clock 5CLK that drives the shift register 3 in FIG. 2 generally has a /dot display time t in FIG.
, pulses with the same period as , are used.

As shown in the video amplifier output in Fig. 3, CR
The video amplifier in the T display unit 1-5 requires a fall time t and a rise time tr of several nS, for example, SNS, depending on its operating characteristics.

However, in the case of high resolution, the number of display dots on 7 screens increases, so the /dot display time 1d is, for example, gns
becomes smaller like

Therefore, when this/dot display time t becomes smaller than a certain value, in the shadow of the falling and rising times, t in Fig. 3
The actual light emitting time of the dot shown in dI is insufficient.

That is, CR
A problem arises in that sufficient time is not available to generate the T phosphor, making it impossible to display the desired dandruff r image.

And in order to solve such problems.

It is necessary to use a video amplifier with a short response time.
There was an inconvenience that the result was an open side.

Therefore, in the CRT display control device of the present invention,
By solving these inconveniences due to the response characteristics of conventional video amplifiers and adding simple means, it is possible to secure sufficient time for displaying independent/dots even with conventional video amplifiers, thereby achieving high performance. ) ψr image resolution; Configuration To this end, in the CRT display control device of the present invention, display data read from the display memory is input in parallel and serially input. A pulse having a period of /rl (where n is a positive integer) of the dot display time is used as a shift clock to drive a shift register that outputs a video signal. A video signal is generated by outputting from the terminal and performing OR processing on both outputs.

FIG. 7 is a diagram showing an embodiment of the CRT display controller 1 of the present invention, and is a block diagram showing a shift register and its peripheral circuits. The symbols in the drawing are the same as in FIG. 2, and g is an OR gate circuit and 5CLK' is 5C.
Indicates the shift clock of //n of LK.

In the embodiment shown in FIG. 7, the output Qm of the final stage of the shift register 3 and the output Qm-s of the seven stages before it are input to the OR gate circuit g and subjected to OR processing, and the video signal VIDEO is generated from the OR gate circuit. is configured to be

FIG. 5 is a time chart showing the correspondence between the video signal generated by the CRT display jli control device of the present invention and sent to the video amplifier, and the output of the video amplifier, with the percentage shown in the figure. The code in the drawing is the third
It is the same as that shown in the figure, and t and 1' indicate the actual light emission time of the phosphor/dot, and td2' indicates one hour of non-display (non-light emission time) of the /dot.

In the CRT display control device of this invention.

Shift clock 5 that drives shift register 3 in figure A”
CLK', //11( of dot display time td)
However, a pulse with a period of (n is a positive integer) is used,
In the case of FIG. S, driving is performed with pulses having a cycle of //.

Therefore, as shown in FIG.
The 1 output and the 9m output are shifted by a time of // the dot display time 1d. Therefore, the video signal generated from the OR gate circuit g in FIG. It will be outputted with a lot of length.

That is, the dot display time t in the conventional case is as follows.

In the case of this invention, it is (/+'/a)''+1.

As a result, the light emitting time tdI' of the phosphor/dot shown in the video amplifier output in FIG. 5 becomes longer than tdl in FIG. A large amount of luminous energy will be given.

Therefore, even with a video amplifier having conventional response characteristics, sufficient independent/dot display time can be ensured and high-resolution display can be achieved.

In the case of FIG. The light area is not proportional to 1 hour td□' and t,2'.

Therefore, on an actual CRT screen, the light-emitting area of the / dot is smaller than the light-emitting time td, /, and conversely, the non-light-emitting area of the / dot is larger than the non-display time td,'. Therefore, the light-emitting area of the / dot / Non-emission can be determined on the CRT screen, improving resolution.

As described above in detail, in the CRT display 1DII control device of the present invention, display data read from the display memory is input in parallel and output in serial to drive the shift register that generates the video signal. By using a pulse having a period of //n (where n is a positive integer) of the /dot display time as a clock, and outputting it from multiple terminals of the shift register and ORing both outputs, the video I am trying to generate a signal.

In the above embodiments, the period of the shift clock is set to /lI of the dot display time, and the case where the final output of the shift register and the output of the seven stages before it are used is excluded. Shita. However, the period of the shift clock does not necessarily have to be 1/4t. Furthermore, it is not necessary that the number of outputs from the shift register is Y, and it is also possible to use a plurality of other outputs.
It is not limited to the case of the example.

Effects Therefore, with the CRT display control sub-control device of the present invention, sufficient display time for seven independent dots can be ensured without being constrained by the rise and fall characteristics of the video amplifier in the CRT display unit. As a result, the apparent resolution is improved and high-resolution display becomes possible.Furthermore, the means added for this purpose are extremely simple, so it has excellent effects such as being advantageous in terms of cost. can get.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing an example of the main configuration of a CRT display control device conventionally used in computer application systems; FIG. 2 is a block diagram showing a detailed configuration example of the shift register shown in FIG. 1; FIG. 3 is a time chart showing the correspondence between a conventional video input signal applied to a video amplifier in a CRT display unit and its output signal, and FIG. 7 is a diagram showing an embodiment of the CRT display control device of the present invention. , and FIG. S are time charts showing the correspondence between the video signal generated by the CRT display control device of the present invention shown in FIG. 7 and sent to the video amplifier, and the output of the video amplifier. In the drawings, / is a CRT controller, `` is a display memory, `` is a shift register, `` is an address decoder &
CRT display unit in the evening. 7 shows the system bus-4-6 Patent ♂1-Applicant Ricoh Co., Ltd. -VDATA

Claims (1)

[Claims] In a CRT display control device having a shift register in which display data read from a display memory is input in parallel and output in serial to generate a video signal, the /dot display time // is used. (where n is a positive integer), and a means for outputting from a plurality of ☆1; A CRT display characterized in that the shift register is driven to generate a video signal! t
i control device.