JPS61278889A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control circuit for displaying characters and symbols in a raster scan method on a display device using a cathode ray tube or the like.

[Conventional technology]

FIG. 4 is a block diagram showing the basic configuration of the display device.

In the figure, (10) is a data input/output control circuit, and a refresh memory (11) for coded character data.
Control input/output to. (12) is a basic control circuit that generates timing signals necessary for display control in synchronization with a horizontal synchronization signal and a vertical synchronization signal of raster scan in a display device (not shown). (13) is an address control circuit which generates an address signal for accessing the refresh memory (11) in synchronization with the timing signal generated by the basic control circuit (12). Refresh memory (
11) stores character and symbol codes, with each character stored in one address position. (14) is a character pattern generation circuit, which uses character and symbol codes as addresses,
A pattern memory (not shown) in which the dot pattern of the character or symbol is stored is read out to generate a dot pattern of the character.

The character code read from the refresh memory (11) by the address signal from the address control circuit (13) becomes the address for the pattern memory of the character pattern generation circuit (14), and the dot pattern of that character is read out.

(15) is an output control circuit, and a character pattern generation circuit (1
4) The character dot pattern read out from the basic control circuit (12) is converted into a bit-serial video signal to be displayed using a raster scan method and outputted in response to a timing signal from the basic control circuit (12). The refresh memory (11) stores control signals in addition to character codes, and when the control (e) signal is read out, this signal is sent to the output control circuit (
15).

FIG. 5 is a block diagram showing the conventional circuit configuration of the address control circuit (13) in FIG. is a matching circuit. In addition, in the figure, A, B, C, DVi each have different constants, G
, JVi are switching control signals, H is a load signal for the address counter fl), H is an increment signal for the address counter +1), and a KU display end signal.

Next, FIG. 6 is an explanatory diagram showing a part of the display on the display surface of the display device, in which a small rectangular fold is a one-dot pixel.
The hatched pixel corresponding to 1 bit output from the character pattern generation circuit (14) represents black and has logic "1".
", and other pixels represent white and the logic "
It is considered that this corresponds to the bit "0". The numbers 1 to 8 on the left side of the figure represent all raster scan scanning line numbers, (60), (
62) Fi display section (61) and (63) indicate character spacing. The figure shows four characters located between the i-th row, the il1-th row, the first column, and the j+1-th column.

In the example shown in FIG. 6, the pattern memory of the character pattern generation circuit (14) has a memo IJ' of 5×7=35 bits for one character, and the bit corresponding to the black pixel in FIG. Indicates when the signal is stored. In addition, the case where the character spacing is one dot in both the row and column directions is shown.

FIG. 7 shows signals output from the output control circuit (15) corresponding to FIG. 6, and the numbers on the left are the scanning line numbers of the raster scan. However, FIG. 7 shows only the output of the portion corresponding to the i-th row of FIG. 6.

Figure 8 is an explanatory diagram showing an example of the display displayed by controlling the circuit in Figure 5.
It is assumed that only row display is shown, and characters are displayed in each row and 10 columns.

Figure 9 shows the refresh memory (
11).

The operation of the circuit shown in FIG. 5 will be explained with reference to FIGS. 6 to 9. First, the basic control circuit (12) that detected the display position
An address is loaded into the address counter (1) by the signal I from the address counter (1). Since the multiplexer 1 (2) selects the constant Ak, which is the start address of the first row, by the signal J from the basic control circuit (12), the address counter (1) is loaded with OO, which is the content of the constant A. Then, the code of the character A in the first row and first column is read out. Then, for each character, the contents of the address counter fil are incremented by the value l by the signal H, and 00, 01, 02...(1
Displayed in 0-decimal notation (the same applies hereafter). On the other hand, the basic control circuit (
The multiplexer 2 (3) selects the constant B (in this example, its value is 09), which is the end address of the first row, by the signal G from the address counter (12).
) becomes 09, the coincidence circuit (4) sends a display end signal K to the basic control circuit (12). Returning to the content Vioo of the address counter (1), if this is repeated for eight rask scanning lines, the display of the first line is completed. Next, when the basic control circuit (12) detects the display position of the second line, the multiplexer 1 (2) selects the constant C which is the start address of the second line by the signal J, and the signal engineer selects the constant C which is the start address of the second line. The value of the constant C of the starting address of lO is loaded into the total address counter (1). Refresh memory (
The character code of the character stored at address 10 is read from 1). Then, the address counter is incremented by the signal H for each character. Multiplexer 2 (
3) is the second one by the signal G from the basic control circuit (12).
Constant D′f, which is the display end address of the row, is selected, and if the address signal of the address counter [11 reaches the constant value 19, the matching circuit (4) will change the display end address of the second row. Sends a signal In which is an end signal. When this is repeated by eight scanning lines, the display of the second line is completed. In this way, one screen's worth of display is performed.

[Problem that the invention seeks to solve]

As described above, in conventional display control circuits, the number of columns in one row is fixed as a constant during initial hardware design, and when displaying multiple rows, the refresh memory address corresponding to the starting point of each row is fixed. However, depending on the display format, there is a problem in that memory must be provided even at address locations where data is not written.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a display control circuit that can efficiently use refresh memory.

[Means for solving problems]

In this invention, the display end address of each row can be arbitrarily set to 5KL by program control, and the number of columns in each row can be arbitrarily set while using the refresh memory efficiently.

[Effect]

Since the display end address can be set arbitrarily, the number of displayed characters in each line can be changed arbitrarily.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and corresponds to FIG. 5 showing a conventional circuit. The same reference numerals as in FIG. shows. (5) is the memory device i11, +6) is the memory device 2. +71 is an address latch. Further, L indicates a clear signal that sets the contents of the address latch (7) to 0, and a load signal to the MH address latch (7).

Fig. 2 is an explanatory diagram showing an example of a display displayed under the control of the circuit shown in Fig. 1, and corresponds to Fig. 8, but an example in which 7 characters are displayed on the first line and 13 characters are displayed on the second line. shows. Figure 3 is the second
The address of the refresh memory (11) corresponding to the display in the figure is shown. The address where the character code of the character H displayed in the second row and first column is stored is 07, and the address in which the character code of the character H displayed in the second row and first column is stored is 07.
Since the character code for the letter G displayed in the last column is the number following the stored address 06, it is displayed in two lines, but it is stored in a continuous memory area in the refresh memory (11). represent.

Next, the operation of the circuit shown in FIG. 1 will be explained. First, the content of the address latch (7) is changed to the address counter fl by a signal from the basic control circuit (12) that has detected the display position.
) is loaded. Prior to this, the basic control circuit (12
), the contents of the address latch (7) are set to 00, so OO is input as the initial value of the address counter (1), and the character code of character A stored at address OO is read out. . Every time one character is read, the content Vil of the address counter fil is read from the signal HK.
increase by increments.

Memory device 1 (5) is preset to the numerical value 06 by program control, and memory device 2 (6) is similarly set to the numerical value 19. On the other hand, the signal G from the basic control circuit (12) causes the multiplexer (3) to
outputs the contents of the memory device 1 (5), so when the address signal from the address counter (1) reaches the value 06, the coincidence circuit (4) outputs the display end signal K and the basic control circuit (12 ). Rusk scan this #i! After repeating this for eight lines, the display of the first line ends. At this time, the basic control circuit (12) outputs the signal M, and the address signal (i.e., the numerical value 06)'i of the output of the address counter fil.
Store in address latch (7). Next, the basic control circuit (
12) Loads the final address of the first line (number 06) into the address counter (1) by the signal engineer, and adds the entire number 1 to the contents of the address counter (1) using the signal H (as a result, the number becomes Vi07). ) start displaying.

Then, the content of the address counter fil becomes 1 due to the signal H.
The value increases by l for each character. Multiplexer (3)
The memory device 2 (6) is controlled by the signal G from the basic control circuit.
), the content is 19, so
Address signal from address counter (1) is number 19
Then, the coincidence circuit [41Vi sends the signal which is the display end signal of the second line to the basic control circuit to 1f! :send.

By repeating this for eight raster scanning lines, the display of the second line is completed. In this way, one screen's worth of display is performed.

In addition, in the above embodiment, as shown in FIG. 6, the 9 vertical character spaces (63) are taken as one raster scanning line, and this is included in one line of character display to form 8 raster scanning lines. , the vertical character spacing (63), that is, the line spacing, can be set arbitrarily, and it is clear that even in that case, the entire circuit of FIG. 1 can be applied as is.

Furthermore, in the above embodiment, a match signal is output at the final address of the displayed character and the display of that line is completed, but in this type of display circuit, there is a time delay from the address determination to the output of the display output. Since there is room for , the final address +1
It is also possible to send all the match signals and end the display with the value .

Further, in the above embodiment, a two-line display was described for convenience of explanation, but it goes without saying that the present invention can be applied to a display of three or more lines.

〔Effect of the invention〕

As described above, according to the present invention, the number of characters that can be displayed in one line can be programmed, so refresh memory can be saved in terms of hardware configuration, and especially in integrated circuits, the chip area can be reduced, resulting in cost savings. You can get the effect of down. Another advantage is that display programs can be freely programmed without being restricted by hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a display displayed by controlling the circuit in FIG. 1, and FIG. 3 is a refresh corresponding to the display in FIG. 2. 4 is a block diagram showing the basic configuration of the display device, FIG. 5 is a block diagram showing the conventional circuit configuration of the address control circuit in FIG. 4, and FIG. 6 is a block diagram showing the basic configuration of the display device. An explanatory diagram showing a part of the display on the display screen, FIG. 7 is a waveform diagram showing signals output from the output control circuit corresponding to FIG. 6, and FIG. FIG. 9 is an explanatory diagram showing an example of a display shown in FIG. 8; FIG. (1) address counter, (3) multiplexer, (
4)・ is a matching circuit, (7) is an address latch, (ii)
Fresh Memo IJ, (12) is the basic control circuit, (
13) is an address control circuit, (14) is a character pattern generation circuit, and (15) is an output control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a display control circuit in which a character pattern generation circuit generates a character dot pattern corresponding to a character code read from a refresh memory, and the generated dot pattern is displayed by a raster scan method, the display control circuit comprises: means for storing character codes in the refresh memory at address positions according to the display order regardless of line classification; an address counter for generating an address signal for reading the refresh memory; and the above as an initial value of the address counter. Means for setting a numerical value representing the address of the character code to be read first from the refresh memory, and incrementing the contents of the address counter by 1 each time one data of the character code is read, the address signal from the address counter being a matching circuit serving as one input; means for inputting a numerical value representing the address in the refresh memory of the last character of the currently displayed line as the other input of the matching circuit; means for outputting a display end signal when a match with an input is detected, a means for processing this display end signal to detect a change point in the display line of characters, and an address to which the display end signal is output at the time of the change; A display control circuit comprising: an address latch for latching a signal; and means for setting a value obtained by adding a value 1 to the contents of the address latch as an updated initial value of the address counter after changing the display line.