JPS6225787A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control circuit for displaying characters and symbols in a raster scan method on a display device using a cathode ray tube or the like.

[Conventional technology]

FIG. 4 is a block diagram showing the basic configuration of the display device.

In the figure, (10) is a data input/output control circuit which is coded to refresh the next character data! J (1
1) Control input/output to. Reference numeral (12) denotes a basic control circuit that generates timing signals necessary for display control in synchronization with a horizontal synchronization signal and a vertical synchronization signal for raster scanning in a display device fi (not shown). (13) is an address control circuit which generates an address signal for accessing the refresh memory (11) in synchronization with a timing signal generated by the basic circuit (12). Refresh memo! J(11) stores character and symbol codes, one character per address position. (14)
1 is a character pattern generation circuit which uses the code of a character or symbol as an address to read out a pattern memory (not shown) in which the dot pattern of that character or symbol is stored and generates a character dot pattern.

The character code read from the refresh memory (11) by the address signal from the address control circuit (13) becomes the address for the pattern memory of the character pattern generation circuit (14), and the dot pattern of that character is read out.

(15) is an output control circuit, and a character pattern generation circuit (1
4) The character dot pattern read out from the basic control circuit (12) is converted into a bit-serial video signal to be displayed using a raster scan method and outputted in response to a timing signal from the basic control circuit (12). Refresh memo IJ (11)
In addition to the Kf1 character code, a control signal is also stored, and when the control signal is read out, this signal is sent to the output control circuit (
15).

FIG. 5 is a block diagram showing the conventional circuit configuration of the address control circuit (13) in FIG. 4. In FIG. 5, +11 is an address counter, (2) is multiplexer 1, (3) is multiplexer 2, and F41 is It is a matching circuit. In addition, in the figure, A, B, C, and D are different constants, G,
J is the switching control signal, ■ is the address counter (1
), an increment signal for the Htl address counter (1), and K a display end signal.

Next, FIG. 6 is an explanatory diagram showing a part of the display on the display screen of the display device, in which a small rectangular square is a one-dot pixel.
Corresponding to 1 bit output from the character pattern generation circuit (14), the hatched pixel represents white and has logic "1".
”, and other pixels represent black and the logic “
It is considered that this corresponds to the bit "O". The numbers 1 to 8 on the left side of the figure represent the scanning line numbers of raster scan, (60), (
62) Fi display section (61) and (63) indicate character spacing. The figure shows four characters located between the i-th row, the i+1-th row, the first column, and the j+1-th column.

In the example shown in FIG. 6, the pattern memory of the character pattern generation circuit (14) has a memory of 5×7-35 bits for one character, and the bit corresponding to the white pixel in FIG. 6 has a logic “1” signal. Indicates when it is stored. In addition, the case where the character spacing is one dot in both the row and column directions is shown.

FIG. 7 shows signals output from the output control circuit (15) corresponding to FIG. 6, and the numbers on the left are the scanning line numbers of the raster scan. However, FIG. 7 shows only the output of the portion corresponding to the i-th row of FIG. 6.

FIG. 8 is an explanatory diagram showing an example of a display displayed by the control of the circuit shown in FIG. Suppose that

Figure 9 shows the refresh memory (
11).

Next, the operation of the circuit shown in FIG. 5 will be explained with reference to FIGS. 6 to 9. First, a signal from the basic control circuit (12) detecting the display position fit causes the address counter fl
+The hair address is loaded.

Multiplexer 1 (2) selects constant A, which is the start address of the first row, by signal J from basic control circuit (12), so OO, which is the content of constant A, is loaded into address counter (1). Then, the code of the character A in the first row and first column is read out. Then, for each character, the contents of the address counter (1) are incremented by 1 by the signal H, and 00,
01, 02... (displayed in decimal system, same below).

On the other hand, the multiplexer 2 (3) selects the constant B (in this example, the value is 09), which is the end address of the first row, in response to the signal G from the basic control circuit (12).
When the address signal from the address counter (1) reaches 09, the coincidence circuit (4) sends a display end signal K to the basic control circuit (12). The content of the address counter (1) is loaded with 00 by the signal I and returns to 00, but when this is repeated for eight rask scanning lines, the display of the first line is completed. Next, the basic control circuit (12) controls the display position If of the second line.
, the multiplexer 1[21tl signal J selects the constant C, which is the start address of the second line, and the signalman uses it! ll 10 of the value of constant C at the start address of the second line
Load it into the address counter (1).

The character code for the character stored at address 10 is read from the refresh memory (11). Then, the address counter is incremented by the signal H for each character. Multiplexer 2 (3) is the basic control circuit (12)
When the address signal of the address counter (1) reaches 19, which is the value of the constant, the match circuit (
4) sends a signal K which is a display end signal for the second line.

When this is repeated for eight scanning lines, the display of the second line is completed. In this way, one screen's worth of display is performed.

[Problem 3 to be Solved by the Invention As described above, in the conventional display control circuit, the number of columns in row f'i1 is fixed as a constant at the time of initial hardware design and cannot be changed. Also, if you want to display multiple lines,
Since the address of the refresh memory corresponding to the starting point of each row is fixed, there is a problem in that depending on the display format, memory must be provided even at address positions where data is not written.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a display control circuit that can efficiently use refresh memory.

[Means for solving problems]

In this invention, the display end signal for each row is generated from a special character code written in the refresh memory, so that the number of columns in each row can be arbitrarily set by program control, and the refresh memory can be used efficiently. This is what I did.

[Effect]

Since special character codes can be written to any address in the refresh memory by a program, the number of displayed characters in each line can be changed arbitrarily.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and corresponds to FIG. 5 showing a conventional circuit. The same reference numerals as in FIG. Show signal. (5) is a matching circuit between the constant E and the output signal from the refresh memory, and (6) outputs the logical sum of the output signal of the matching circuit (5) and the stop signal (7) of the address counter (1). An OR circuit, (7) a stop signal output when the address counter (1) exceeds the address of the refresh memory (11), and (8) an address latch. Also, the contents of the LH address latch (8) t-
A clear signal set to O and a load signal to the MU address latch (8) are shown.

Fig. 2 is an explanatory diagram showing an example of a display displayed under the control of the circuit shown in Fig. 1, and corresponds to Fig. 8, but an example in which 7 characters are displayed on the first line and 13 characters are displayed on the second line. shows. @Figure 3 is the second
The address value of the refresh memory (11) corresponding to the display in the figure is shown. The address where the character code of the character H displayed in the second row and first column is stored is 08, and the address in which the character code of the character H displayed in the second row and first column is stored is 08, and the
The code for the next line break after the letter G to be displayed in the last column is the number that is stored at address 07, so it is displayed in two lines, but it is stored in a continuous memory area in the refresh memory (11). represents that

Next, the operation of the circuit shown in FIG. 1 will be explained. First, the content of the address latch (8) is changed to the address counter (1) by the signal ■ from the basic control circuit (12) that has detected the display position.
) is loaded. Prior to this, the basic control circuit (12
), the content of the address latch (8) is set to 00, so OO is manually entered as the initial value of the address counter il+, and the character code of the character A, which is partially stored at address 00, is read out. , each time one character is read, the address counter changes to 1 by the signal H.
increase by increments.

The character code read from the refresh memory (11) is compared with a constant E, which is a code for successive line breaks, in a matching circuit (5). The address signal from the address counter (1) becomes the number 07, and the refresh memory 17
When the line feed character code constant E read from (11) is sent to the match circuit (5), the match circuit (5) outputs a display end signal, which indicates ORI! ? The signal is sent as a signal via the J path (6) to the basic ffj11 and dir (12).

When these steps are repeated for eight rask scanning lines, the display of the first row is completed. At this time, the basic-J-circuit (12) stores the signal Mk low output and the address signal (ie, the numerical value 07) of the output of the address counter (1) in the address latch (8).

Next, when the basic control circuit (12) detects the next display position, it sends the final address (number 07) of the first line by signal I.
t is loaded into the address counter (1), and the value 1 is added to the contents of the address counter ill by the signal H (as a result, the value becomes 08) to start displaying. Then, the contents of the address counter (1) are incremented by 1 for each character by the signal H. When the range of address counter tllU and refresh memory (11) is exceeded, the stop signal line (
7) A stop signal is sent to the top, and this is sent as a signal to the basic control circuit (12) through the OR circuit (6).

The display of the second line is completed by repeating this by eight rask scanning lines. In this way, one screen's worth of display is performed.

In the above embodiment, as shown in FIG. 6, the vertical character spacing (63) is one rask scanning line, and this is included in one line of character display to form eight rask scanning lines. It is clear that the vertical character spacing (63), that is, the line spacing, can be set arbitrarily, and even in that case, the circuit of FIG. 1 can be applied as is.

In addition, in the above embodiment, a match signal is output at the final address of the display character, the display of that line is completed, and the address is latched to the address latch. However, in this display circuit, the address is determined. Since there is ample time between the display output and the display output, it is also possible to latch the value 1 in the final address and use it as the start address for the next display.

Further, in the above embodiment, a two-line display was described for convenience of explanation, but it goes without saying that the present invention can be applied to a display of three or more lines.

Also, although we have explained that the display of the last line ends with the display end signal from the address counter, if you make sure to include a line feed character code in every line, you can
The OR circuit (6) shown in the figure may be omitted entirely, and the output of the coincidence circuit (15) may be sent as a signal to the basic control circuit (12).

〔Effect of the invention〕

As described above, according to the present invention, the number of characters that can be displayed in one line can be programmed, so refresh memory can be saved in terms of hardware configuration, and especially in integrated circuits, the chip area can be reduced, resulting in cost savings. You can get the effect of down. Another advantage is that display programs can be freely programmed without being restricted by hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention 1li111, FIG. 2 is an explanatory diagram showing an example of a display displayed by controlling the circuit in FIG. 1, and FIG. 3 is a refresh corresponding to the display in FIG. 2. An explanatory diagram showing memory addresses, Fig. 4 is a block diagram showing the basic configuration of the display device, wJs diagram is a block diagram showing the conventional circuit configuration of the address control circuit of m4 diagram, and Fig. 6 is the display surface of the display device. An explanatory diagram showing a part of the above display, FIG. 7 is a waveform diagram showing a device composed of an output control circuit corresponding to FIG. 6, and FIG. 8 is a waveform diagram displayed by control of the circuit in FIG. 5. FIG. 9 is an explanatory diagram showing an example of a display; FIG. 9 is an explanatory diagram showing an address of a refresh memory corresponding to the display of FIG. 8; (1) is an address counter, (5) is a matching circuit, (6)
is an OR circuit, (7) is a stop signal line, (8) is an address latch, (11) is a refresh memory IJ, (12)
is the basic control circuit, (13) is the address control circuit, and (14) is the basic control circuit.
) is a character pattern generation circuit, and (15) is an output control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A character pattern generation circuit generates a character dot pattern corresponding to the character code read from the refresh memory, and in a display control circuit when displaying the generated dot pattern using the raster scan method, means for storing a character code in the refresh memory at an address position according to the display order and a line feed code at an address position where a line feed is to be executed in display; and an address signal for reading the refresh memory. Address counter to be generated. Set a numerical value representing the address of the character code to be read first from the refresh memory as the initial value of this address counter, and change the contents of the address counter by 1 each time one character code data is read. means for incrementing; a matching circuit whose one input is the output of the refresh memory selected by the address signal from the address counter; means for inputting the line feed code as the other input of the matching circuit; means for outputting a display end signal when detecting a match between the input of and the other input; processing this display end signal to detect a change point in the display line of characters; and outputting the display end signal at this change point; an address latch for latching an address signal output from the address signal; and means for setting a value obtained by adding a value 1 to the contents of the address latch as an initial update value of the address counter after the display line is changed. display control circuit. (2) The means for outputting the display end signal includes an OR circuit that outputs the logical sum of the output of the matching circuit and the stop signal output when the address counter exceeds the memory display area as the display end signal. A display control circuit according to claim 1, characterized in that: