JPS5845715B2 - Graphics Hiyoji Souchi - Google Patents

Description

[Detailed description of the invention] The present invention relates to graphic display devices.

More specifically, the present invention relates to a graphic display device that can arbitrarily enlarge or reduce the scale of a scale when displaying numerical data in a graph.

Graphic display devices using CRTs are often used as terminals for digital data processing devices.

When displaying numerical data as a graph using such a device, it would be convenient if the scale of the scale could be freely enlarged or reduced.

An object of the present invention is to provide a graphic display device that can arbitrarily enlarge or reduce the scale of a graph.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a normal raster scan type color graphic display device, which includes a control circuit 11.
, a refresh memo January 2, a pattern generator 13, a synchronous brightness control circuit 14, a timing circuit 15, and a CRT 16.

2 is a scale conversion device, in which 21 is a data memory, 22 is a control section, 23 is a clock pulse generator, 24 is a data address generation section, and 25 is an address conversion section.

Data memory 21 stores data y1. to be displayed as a graph on CRTI 6. y2...yn is given from an external computer or the like (circuit) and stored.

The control unit 22 provides the data address generation unit 24 with a read start address a and an address interval d from an external computer, operator operating device, etc. (enclosure) based on the clock pulses provided from the clock pulse generator 23. These values are used to generate the data address generator 24.
generates the read address ai using the following equation.

a s = a + (t 1 ) d
(1) However, i: Clock pulse number, which is equal to the X upper axis direction number on the CRT.

Equation (1) means that storage locations after address a are specified in order at address intervals d.

This address ai is finally given to the data memory 21, and the data Yi stored at that address is read out from the data memory 21.

Data reading is performed at the closest intervals when d=1, and becomes more sparse as d becomes larger.

Data Yi read from data memory 21 is given to address conversion section 25.

The address converter 25 is provided with a clock via the controller 22.
When the pulse is applied, the address converter 25 calculates the X address interval and Y address interval for writing the position of the display dot on the CRT 16 into the refresh memory 12 using the following equations.

However, AI...dot spacing in the X direction, B1...X
Axis start point address, A2...Dot spacing in the Y direction, B
2... Y-axis starting point address, the control circuit 11 uses this to refresh the memory 12.
A dot signal is written to the specified address (ξi, ηi) within.

At this time, dot color signals are also written according to the contents of the data memory 21.

When the contents of the refresh memory 12 written in this way are displayed on the CRT 16, depending on how the value of d is determined, it is also possible to display an overview of the data over a 24-hour period as shown in Figure 2.1. As shown in Figure 2, it is also possible to precisely display the transition of data for the first two hours.

As described above, according to the present invention, numerical data can be displayed in a graph of any scale, which is very convenient in practice.

It should be noted that the present invention is not limited to the CRT graphic display device of the raster scan type.

[Brief explanation of drawings]

FIG. 1 is a conceptual block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the apparatus shown in FIG. 1...Rusk scan/CRT graphic display device, 2...Graduation scale conversion device.

Claims (1)

[Scope of Claims] 1. A graphic display device having a refresh memory and its write control circuit and displaying an image based on information written in the refresh memory, comprising: a clock pulse generator, a clock pulse generator, a series of addresses; A data memory that stores a series of numerical data, and a read address of the data memory is determined by a read start address a given from the outside, an address interval d, and a clock pulse number i given from the clock pulse generator. a data address generation unit that calculates the address using the formula (%) and supplies this address to the data memory as the read address of the data, and the data that is read from the data memory according to the address provided by the data address generation unit. Using Yi and the clock pulse number i given from the clock pulse generator, calculate the X address and Y address using the formula % formula % (however, A1.A2.B1.B2 are constants)
, a display address converter for providing these addresses to a control circuit of the graphic display device as addresses for writing dots into a refresh memory.