JPS6379643U - - Google Patents
Info
- Publication number
- JPS6379643U JPS6379643U JP1986173127U JP17312786U JPS6379643U JP S6379643 U JPS6379643 U JP S6379643U JP 1986173127 U JP1986173127 U JP 1986173127U JP 17312786 U JP17312786 U JP 17312786U JP S6379643 U JPS6379643 U JP S6379643U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- electrode metals
- conductor pattern
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims 3
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 150000002739 metals Chemical class 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
第1図はこの考案の一実施例を示す回路基板の
概略構成図、第2図A,Bは上記回路基板の導体
パターンを連結導体で連結した状態の側面図およ
び部分平面図、第3図はこの種の回路基板に用い
られる電気回路図、第4図は前記電気回路を実現
した従来の回路基板の概略構成図である。 10……回路基板、11……チツプ用導体パタ
ーン、12aないし12n……分離ソース用導体
パターン、13aないし13n……分離ゲート用
導体パターン、14……細線ワイヤ、15……連
結導体、T1〜Tn……MOS FETチツプ、
D0……ソース端子、S0……ソース端子、G0
……ゲート端子。
概略構成図、第2図A,Bは上記回路基板の導体
パターンを連結導体で連結した状態の側面図およ
び部分平面図、第3図はこの種の回路基板に用い
られる電気回路図、第4図は前記電気回路を実現
した従来の回路基板の概略構成図である。 10……回路基板、11……チツプ用導体パタ
ーン、12aないし12n……分離ソース用導体
パターン、13aないし13n……分離ゲート用
導体パターン、14……細線ワイヤ、15……連
結導体、T1〜Tn……MOS FETチツプ、
D0……ソース端子、S0……ソース端子、G0
……ゲート端子。
Claims (1)
- MOS FET等の各半導体チツプのソースお
よびゲート等に対応する電極金属から引き出され
る細線ワイヤが独立してボンデイングされるよう
に、各半導体チツプのそれぞれの電極金属に対応
するように分離形成された複数の導体パターンを
備えたことを特徴とする半導体装置用回路基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986173127U JPS6379643U (ja) | 1986-11-11 | 1986-11-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986173127U JPS6379643U (ja) | 1986-11-11 | 1986-11-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6379643U true JPS6379643U (ja) | 1988-05-26 |
Family
ID=31110296
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986173127U Pending JPS6379643U (ja) | 1986-11-11 | 1986-11-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6379643U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1056029A (ja) * | 1996-08-12 | 1998-02-24 | Toshiba Corp | 半導体装置およびその計測方法 |
JP2006149195A (ja) * | 1995-06-21 | 2006-06-08 | Cree Inc | 変換器回路、少なくとも1つのスイッチング・デバイスを有する回路および回路モジュール |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5743453A (en) * | 1980-08-28 | 1982-03-11 | Nec Corp | Integrated circuit |
JPS5952860A (ja) * | 1982-09-20 | 1984-03-27 | Mitsubishi Electric Corp | 半導体集積回路装置 |
-
1986
- 1986-11-11 JP JP1986173127U patent/JPS6379643U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5743453A (en) * | 1980-08-28 | 1982-03-11 | Nec Corp | Integrated circuit |
JPS5952860A (ja) * | 1982-09-20 | 1984-03-27 | Mitsubishi Electric Corp | 半導体集積回路装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006149195A (ja) * | 1995-06-21 | 2006-06-08 | Cree Inc | 変換器回路、少なくとも1つのスイッチング・デバイスを有する回路および回路モジュール |
JPH1056029A (ja) * | 1996-08-12 | 1998-02-24 | Toshiba Corp | 半導体装置およびその計測方法 |
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