JPS6379409A - Digital filter device - Google Patents

Abstract

PURPOSE:To improve the calculation accuracy of a filter by storing a preserved signal value while dividing it into a present sampling value and a preceding sampling value and making a substantial bit number longer so as to eliminate missing of bits. CONSTITUTION:A CPU 23 applies computing processing sequentially according to an instruction stored in an instruction storage section 24. The instruction storage section 24 consists of a ROM, in which the calculation processing of algorithm of the digital filter is stored. An input section 21 samples an input signal and inputs a preceding sampling as required to an information storage section 25. The CPU 23 uses a data of the information storage section 25 comprising RAM to apply filter calculation/processing and outputs (22) the result. In the digital filter device comprising an input section 21, the output section 22, the CPU 23, the instruction storage section 24 and the information storage section 25, the contents of the instruction storage section 24 are constituted properly to form the digital filter. Thus, missing of bits is eliminated and the accuracy of filter is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a recursive digital filter having required filter characteristics, and in particular to a digital filter with good calculation accuracy and short calculation time from input to output. The present invention provides a filter device.

Prior Art In recent years, using microprocessors in control devices,
PI control filters have come to be configured digitally. Here, P means proportional action and ■ means integral action. As such a digital filter for Pl control, a recursive digital filter can be used. for example,
A PI control filter having a pulse transfer function G (z) shown in (112) below exhibits integral characteristics in a low frequency region, and is suitable for improving the characteristics of a control device (not publicly known).

Here, z −1 represents a delay of one sampling time,
k is a constant value coefficient. FIG. 3 shows the frequency characteristics of the digital filter of formula (1) approximated by a broken line. In the low frequency region below the corner frequency fc in Fig. 3, the gain (G(z)
] has a frequency characteristic of -6 dB10 ct, and the lower the frequency, the thicker the gain (the integral characteristic becomes. Also, in the frequency region above the corner frequency fc, the gain is a constant value (approximately 0 dB). It has a proportional characteristic.

(1) The second coefficient is a constant determined by the sampling time and the corner frequency fc in FIG. In a PI control filter used in a control device, the coefficient has a value sufficiently smaller than 1. For example, sampling time T s = 1 (msec), corner frequency f c
When =10 (fiz), k#ν'=0.062
It becomes 5.

Next, an example of a method for calculating the PI control filter of equation (1) will be described with reference to the flowchart of FIG. 4. In FIG. 4, Xi and yi are the new input signal value and the saved signal value, respectively, and xi-1+yi-I are the input signal value and the saved signal value, respectively, one sampling time before. Here, each signal value is a real number or an infinitely long digital value.

(31) <Block 31> Sample a new input signal value, X,.

(32) <Block 32> A new stored signal value yi is calculated by the following equation.

Y i = Y ;-+ +Xi Xi-+
” kxi ---・----[2) (33) <Block 33> Output the stored signal value yi.

(34) <Block 34> Let Xi and y be Xl-1 and y8-1, respectively.

(35) <Block 35> After a delay until the next sampling point, the operation moves to (31).

By repeating and calculating the operations (31) to (35) above, the characteristics of the PI control filter in equation (1) can be accurately realized.

Problems to be Solved by the Invention However, in reality, the digital values that can be processed by the microprocessor have a finite bit length and can only perform calculations with finite precision. Therefore, a truncation error occurs, which deteriorates the characteristics of the digital filter and adversely affects the control device. In particular, the above formula (1)〇P
Since the I control filter has integral characteristics, the effects of truncation errors appear cumulatively. Regarding this, 16
A case will be described in which a bit-length microprocessor is used to execute the flowchart in FIG. however,
Here, it is set to -2-4.

First, as the first method, y
It is conceivable that , yi, , l are each stored and calculated using one word of digital value having a length of 16 bits. Here, it is assumed that in a 16-bit digital value, the most significant bit is a sign bit, and negative numbers are expressed by two's complement. That is, if a 16-bit digital value is considered an integer, a numerical value from -32768 to 32767 can be expressed. At this time, kxH of the digital filter
−, can be calculated using arithmetic right shift. Here, a 1-bit arithmetic shift to the right substantially corresponds to 1/2. Therefore, when K=2-', a 4-bit arithmetic right shift is performed. However, since Xl-1 and kx-1 are expressed by a finite number of bits (16 bits), if a 4-bit arithmetic right shift is performed in the calculation of kxi-, the information for the lower 4 bits is Bit loss (a phenomenon in which lower bit values are lost) occurs. This significantly reduces the calculation accuracy of the filter. In particular, since the PI control filter is an integral type filter, the influence of bit loss accumulates, significantly deteriorating the filter accuracy. As a result, when used in a control device, control performance deteriorates.

In order to prevent such deterioration in calculation accuracy, a second method is to use two words of 16 bits to effectively calculate 3
Express yi and Yi-+ as 2-bit digital values,
It is conceivable to perform filter calculations.

However, in such a case, calculations involving both the upper and lower words occur, making the calculations extremely complicated. For example, when a carry or a carry down occurs from a lower word to a higher word, there are four types of 32-bit digital value: positive number carry, positive number carry down, negative number carry, and negative number carry down. It becomes necessary to determine which of the cases is the case. This determination requires many comparative calculations and conditional branches. As a result, the disadvantage is that the calculation time becomes very long. The calculation time from the input to the output of this PI control filter corresponds to the control time delay of the control device. When the control time delay becomes large, the control gain must be reduced in order to ensure the stability of the entire control device. Therefore, the calculation time of the PI control filter is required to be as short as possible.

The present invention takes these points into consideration and provides a digital filter that shortens the calculation time from input to output while improving calculation accuracy.

Means for Solving the Problems The present invention includes an input means for obtaining an input signal value of n-bit length for each sampling period, and an output operation for performing an arithmetic operation on the input signal value and a first stored value to obtain an output signal value. means for outputting the output signal value; and a first digital value having an n-bit length by performing an arithmetic operation on a value corresponding to the input signal value at the current or previous sampling time and a second stored value. a first arithmetic means for obtaining the first digital value, and substantially J bits (here, J is an integer such that 1≦Jon);
a second arithmetic means for obtaining an n-bit long second digital value which is arithmetic right-shifted; and an n-bit third digital value representing an arithmetic composite value of the first stored value and the second digital value. a third calculating means for calculating the third digital value; a first updating means for setting the third digital value as a new first stored value;
The contents of the lower J bits of the digital value are matched, and the upper (n-J) from the most significant bit to the (J+1)th bit are
a fourth arithmetic means for obtaining a fourth digital value having an n-bit length in which each bit value is set to the same value as the sign bit of the first digital value; The above problem is solved by using a digital filter device that is equipped with a second updating means for updating the value.

Operation In the present invention, with the above configuration, the stored signal value is stored separately into the first stored value and the second stored value, so the actual bit length of the stored signal value is longer than n bits. This results in no bit loss or very little bit loss. As a result, the accuracy of filter calculations is improved. In addition, since the first stored value and the second stored value are each signed digital values, a value equal to or higher than the (J+l)th bit of the operation result of the second stored value and the input signal value is set as the first stored value. It becomes easy to add and subtract. Furthermore, the input signal value and the first
Since the output signal value is obtained by simply performing arithmetic operations on the stored values, the calculation time from input to output is extremely short.

Embodiment An embodiment of the digital filter according to the present invention will be described below with reference to the drawings.

FIG. 2 shows a basic configuration diagram of the hardware of the digital filter device of the present invention. The central processing unit 23 has an instruction storage unit 24
Calculations and processing are performed sequentially according to the instructions stored in the .

The instruction storage unit 24 is a ROM (ROM: ReadOnl).
y Memory), and stores the calculation processing algorithm of the digital filter. Input section 2
1 samples an input signal such as a detection signal of a control device, converts it into a 16-bit digital value, and sends it to the central processing unit 2.
Enter 3. In the central processing unit 23, RAM (RAM: R
Filter calculations and processing are performed using the information storage unit 25 configured with a memory (andam access memory), and the calculation results are sent to the output unit 22. The output signal value sent to the output unit 22 is used as a control signal for the control device. Such a human resources department 21. Output unit 22°, central processing unit 23 (microprocessor), instruction storage unit 24. In the digital filter device including the information storage section 25, by appropriately configuring the contents of the instruction storage section 24, it is possible to realize a digital filter having the pulse transfer function G (z) of equation (1).

FIG. 1 shows an operation flowchart of the digital filter device of the present invention for realizing the digital filter of formula (1). In the following explanation, it is assumed that the number of processing bits of the central processing unit 23 and the information storage unit 25 is 16 bits, and (11
The coefficient of the equation is 2-'. Also, X, R,
It is assumed that U and W are each 16-bit digital values (n=16), the most significant bit is the sign focus, and negative numbers are expressed as two's complement numbers.

(1) <Block 1: Input block> The input signal value Xi is input as a 16-bit digital value from the input section 2.

(2) <Block 2: Output calculation block> Input signal value X
i and the first stored value Wl stored in the information storage unit 25
(described later) is arithmetic added to obtain an output signal value Yi.

(3) <Block 3: Output block> The output signal value Yi is output to the output section 22.

(4) <Block 4: First calculation block> A digital value R1 is calculated by arithmetic shifting the input signal value Xi by 1 bit to the right. Next, the second stored value W2 (described later) stored in the information storage unit 25 and the digital value R1 are arithmetically added to obtain the first digital value U1.

(5) <Block 5: Second calculation block> A second digital value U2 is obtained by arithmetic right-shifting the first digital value U1 by 3 bits.

(6) <Block 6: Third calculation block> A third digital value U3 is obtained by arithmetically adding the first stored value Wl and the second digital value U2.

(7) <Block 7: First update block> The information storage unit 2 uses the third digital value U3 as the new first stored value W1.
Update and save to 5.

(8) <Block 8: Fourth calculation block> Logical product (AND) of first digital value U1 and hexadecimal value 8000)
) to create a digital value R2. A digital value R3 is obtained by arithmetic right-shifting the digital value R2 by 12 bits. As a result, in the digital value R3, each bit value of the lower 3 bits from the least significant bit (1st bit) to the 3rd bit is O2, and the higher 13 bit values from the 4th bit to the most significant bit (16th bit) The value of each bit of the bit is equal to the value of the sign bit of the first digital value U1.

Next, the first digital value U1 and the hexadecimal value 000711
A logical product (AND) is taken to create a digital value R4. Furthermore, the logical sum (OR) of the digital value R3 and the digital value R4 is
) to obtain the fourth digital value U4. As a result, the contents of the lower 3 bits from the least significant bit to the 3rd bit of the fourth digital value U4 are the same as those of the first digital value U.
1, and the fourth digital value U
Each bit value of the upper 13 bits from the 4th bit to the most significant bit of 4 becomes the same value as the sign bit of the first digital value U1.

(9) <Block 9: Second update block> The information storage unit 2 uses the fourth digital value U4 as the new second stored value W2.
Update and save to 5.

αψ Block 10: Delay block> After delaying until the next sampling point, the operation returns to block 1 (1).

The configuration of this embodiment described above realizes the digital filter of formula (1). This will be explained. First, in blocks 4 to 9, the input signal value Xi
are cumulatively stored as stored signal values (first stored value W1 and second stored value W2). In particular, the 1-bit arithmetic right shift when calculating R1 and the 3-bit arithmetic right shift when calculating U2 cause the coefficient to be multiplied by =21. This stored signal value (W
l and W2), the numerical value of the second stored value W2 is limited to the numerical value represented by the lower 3 bits (block 8 and pro-v).
9), and the first stored value W1 has values larger than that (blocks 4 to 7). 1
The output signal value Yi is calculated by adding the first stored value W1 calculated before the sampling time and the human input signal value Xi (block 2).

As a result, the transfer function from the input signal value Xi to the output signal value Yi matches Equation 11.

In this embodiment configured in this manner, the stored signal value is updated and stored using the first stored value W1 and the second stored value W2. In particular, the first stored value W1 and the second stored value W2 each independently have a sign bit, and the least significant bit of the first stored value W1 numerically corresponds to the fourth-order bit of the second stored value W2. I try to do that. Therefore, the number of bits of the stored signal value is actually 3 bits rather than 16 bits (n=16).
J = 3 bits] longer. As a result, the input signal value
The accuracy of the filter calculation using i is improved, and bit loss can be eliminated or significantly reduced. Note that the stored numerical value of the second stored value W2 is limited to a value that can be expressed by the lower 3 bits (J bits), and larger numerical values are moved to the first stored value W1. Wl and the second stored value W2 complement each other to represent the stored signal value.

In addition, for calculation processing from inputting a new input signal (!Xi) to obtaining a new output signal value Yi, (block 1
From block 3), no comparison calculations or conditional branching are used. Therefore, the computation time during this period is a very small constant value. In particular, the output signal value Y can be calculated simply by arithmetic addition of the input signal value Xi and the first stored value W1 calculated in advance.
Since i is obtained, the computation time from obtaining a new input signal value Xi to obtaining a new output signal value Yi is extremely short. As a result, when the digital filter device of this embodiment is used as a PI control filter of a control device, a filter with small control time delay can be realized.

In addition, in the above-mentioned embodiment in which the pulse transfer function G (z) of equation (1) is realized, if the calculation of R1 in block 4 is changed appropriately, (if the coefficient k of equation 11 is not a negative integer bundle of 2) Furthermore, if it is believed that Xi+W2 will hardly cause overflow, it is also possible to make R1 equal to xi.

-a, an input means for obtaining an input signal value of n bit length for each sampling period; an output calculation means for performing an arithmetic operation on the human input signal value and the first stored value to obtain an output signal value; an output means for outputting an output, and a first calculation means for performing an arithmetic operation on a value corresponding to the input signal value at the present time or a previous sampling time and a second stored value to obtain a first digital value having an n-bit length. , a second arithmetic means for obtaining a second digital value having an n-bit length by substantially arithmetic right-shifting the first digital value by J bits (here, J is an integer such that 1≦Jon); third arithmetic means for obtaining a third digital value of n bit length representing an arithmetic composite value of the stored value and the second digital value; updating means, the contents of the lower J bits from the least significant bit to the third bit are made to match the contents of the lower J bits of the first digital value, and the contents of the lower J bits from the most significant bit to the (J+1)th bit are updated. A fourth method for obtaining an n-bit long fourth digital value in which each bit value of (n-J) bits is set to the same value as the sign bit of the first digital value.
calculating means for converting the fourth digital value into a new second digital value.
If a digital filter equipped with a second updating means for storing values is constructed, the pulse transfer function G of equation (1)
A digital filter having the same or almost the same filter characteristics as (z) can be realized with high precision. Furthermore, the calculation time from input to output is also shortened.

Note that the information storage section 25 in the above-described embodiment uses a register or a RAM memory whose storage contents can be rewritten. Further, in the above embodiment, the input section 21 and the output section 22 are configured independently, but in reality, the input section 21 and the output section 22 may be substituted by the memory or register of the information storage section 25; Needless to say, it is included in the invention. Further, the sampling period may be determined using the detection signal of the control device, etc., and it goes without saying that this is included in the present invention. Furthermore, it is also possible for the central processing unit 23 to perform calculations and processes other than filter calculations during free time. In addition, various modifications can be made without changing the spirit of the present invention.

Effects of the Invention The digital filter device of the present invention has good calculation accuracy and extremely short calculation time from input to output.

Therefore, if a digital filter device that realizes a PI control filter of a control device is constructed based on the present invention, a high-performance control device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the operation of the digital filter of the present invention, FIG. 2 is a basic configuration diagram of the hardware of the digital filter of the present invention, FIG. 3 is a frequency characteristic diagram of the digital filter, and FIG. 4 is a diagram of the frequency characteristics of the digital filter. FIG. 2 is a flowchart diagram illustrating an example of a digital filter calculation method. 21...Input section, 22...Output section, 2
3...Central processing unit, 24...Instruction storage unit, 25...Information storage unit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 2 2+ 23 22 Figure 3

Claims (1)

[Claims] an input means for obtaining an input signal value of n-bit length every sampling period; an output calculation means for performing an arithmetic operation on the input signal value and a first stored value to obtain an output signal value; and an output means for outputting the output signal value. and a first calculation means for calculating a first digital value having an n-bit length by performing an arithmetic operation on a value corresponding to the input signal value at the current point in time or a previous sampling point and a second stored value; a second arithmetic means for obtaining a second digital value having an n-bit length by substantially arithmetic right-shifting the digital value by J bits (here, J is an integer such that 1≦J<n); and a first storage value. and third arithmetic means for obtaining a third digital value of n bit length representing an arithmetic composite value of the second digital value; and a first update for making the third digital value a new first stored value. means, the contents of the lower J bits from the least significant bit to the J-th bit are made to match the contents of the lower J bits of the first digital value, and the contents of the lower J bits from the most significant bit to the (J+1)th bit are - J) fourth arithmetic means for obtaining a fourth digital value of n-bit length in which each bit value of the bits is set to the same value as the sign bit of the first digital value; A digital filter device comprising second updating means for setting a second stored value.