JPS6382012A - Digital filter device - Google Patents

Abstract

PURPOSE:To shorten the time of arithmetic from input to output while improving calculation accuracy by dividing a stored signal value into two parts and storing them as digital values with signs. CONSTITUTION:An input part 21 samples an input signal such as the detection signal of a controller and the sampled value is converted into a 16-bit digital value, which is inputted to a central processing part 23. The central processing part 23 performs filter calculation processing by using an information storage part 25 consisting of RAM and sends the calculation result to an output part 22. The 1st stored value W1 and the 2nd stored value W2 have sign bits individually and the least significant digit bit of the 1st stored value W1 corresponds numerically to the 4th digit bit (Q=4) of the 2nd stored value W2. Consequently, the accuracy of the filter arithmetic using the input signal value is improve and bit absence is eliminated or reduced greatly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a recursive digital filter having required filter characteristics, and in particular to a digital filter with good calculation accuracy and short calculation time from input to output. The present invention provides a filter device.

BACKGROUND OF THE INVENTION In recent years, microprocessors have been used in w control devices to digitally configure filters for PI control. Here, P means proportional action and ■ means integral action. P like this! A recursive digital filter can be used as the control digital filter. For example, a PI control filter having a pulse transfer function G (Zl) shown in equation (1) below exhibits integral characteristics in the low frequency region and is suitable for improving the characteristics of a control device. (Not publicly known) .

1. 4 Here, z4 represents a delay of one sampling time, and k is a constant value coefficient. FIG. 3 shows the frequency characteristics of the digital filter of formula (1) approximated by a broken line. The corner frequency f in FIG. In the following low frequency region, the gain [G (absolute value of Zl)] has a frequency characteristic of -6 dB10 ct, and has an integral characteristic in which the gain becomes larger as the frequency becomes lower. In this region, the gain has a proportional characteristic with a constant value (approximately 0 dB).

The coefficients of equation (1) include the sampling time and the corner frequency f in FIG. It is a constant determined by In the P■ control filter used in the control device, the coefficient has a value sufficiently smaller than 1. For example, sampling time T, = 1 (msec), corner frequency f. −
At 10 (Hz), k#24-0.0625.

Next, a method for calculating the PI control filter of formula +1) will be explained with reference to the flowchart of FIG. Fourth
In the figure, xl and yI are the new input signal value and the saved signal value, respectively, and J-1°yl-1 are the input signal value and the saved signal value, respectively, one sampling point before. Here, each signal value is a real number or an infinitely long digital value.

(31) <Block 31> Sample the new input signal value x1.

(32) <Block 32> A new stored signal value y1 is calculated by the following equation.

yI ””I-1+xI ”I-10k”I-1...
...(2) (33) <Block 33> Output the stored signal value y1.

(34) <Block 34> Let Xi and yl be xl-1 and yl-1, respectively.

(35) <Block 35> After a delay until the next sampling point, the operation moves to (31).

By repeating the above operations (31) to (35) and calculating, the characteristics of the PI control filter of formula +1 can be accurately realized.

Problems to be Solved by the Invention However, in reality, the digital values that can be processed by a microprocessor have a finite bit length and can only perform calculations with finite precision, which results in truncation errors, which can cause problems in digital filters. The characteristics deteriorated and the control device was adversely affected. In particular, PI of the above formula (1)
Since the control filter has an integral characteristic, the influence of truncation errors will accumulate.This will be explained in the case where a 16-bit microprocessor is used to execute the flowchart of FIG. However, here it is set to -24.

First, as the first method, y
It is conceivable that l and yl-1 are each stored and calculated as one-word digital values of 16-bit length. Here, it is assumed that in a 16-bit digital value, the most significant bit is a sign bit, and negative numbers are expressed by two's complement. That is, if a 16-bit digital value is considered an integer, a numerical value from -32768 to 32767 can be expressed. At this time, kXl-1 in equation (2) can be calculated using arithmetic right shift. Here, a 1-bit arithmetic shift to the right substantially corresponds to η times.

Therefore, when k-24, a 4-bit arithmetic right shift is performed. However, since xl-1 and kXl-1 are expressed by a finite number of bits (16 bits), k
If a 4-bit arithmetic right shift is performed in the calculation of Xl-1, a bit drop (a phenomenon in which the lower bit value is lost) of information for the lower 4 bits occurs. This significantly reduces the calculation accuracy of equation (2). In particular, since the PI control filter is an integral type filter, the influence of bit loss accumulates, significantly deteriorating the filter accuracy. As a result, when used in a control device, control performance deteriorates.

In order to prevent such deterioration in calculation accuracy, a second method is to use two words of 16 bits to effectively calculate 3
Express yl and yl-1 as 2-bit digital values,
It is conceivable to calculate equation (2). However, in such a case, calculations involving both the upper and lower words occur, making the calculations extremely complicated. For example, when a carry or a fall occurs from a lower word to a higher word, the 32-bit digital value includes a positive number carry, a positive number carry down, a negative number carry up, and a negative number carry down. It becomes necessary to determine which of the four cases it is. This determination requires many comparative calculations and conditional branches. As a result, the disadvantage is that the calculation time becomes very long. The calculation time from the input to the output of this PI''M filter corresponds to the control time delay of the control device.If the control time delay becomes large, the control gain must be reduced to ensure the stability of the entire control device. Therefore, the calculation time of the PII control filter is required to be as short as possible.

The present invention takes these points into consideration and provides a digital filter that shortens the calculation time from input to output while improving calculation accuracy.

Means for Solving the Problems The present invention provides a digital filter that performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value. , the stored signal value is at least n bits long (where n
is an integer of 4 or more), and the first and second stored values each have a sign bit, and the least significant bit of the first stored value is numerically the 0th-order bit of the second stored value (here, Q is 1<Q
<n integer), and a correction value to the first stored value obtained by arithmetic synthesis operation of the second stored value and the input signal value is input one sampling time or earlier. The above problem is solved by configuring the system to perform calculations in advance using signal values.

A more specific configuration of the present invention includes an input means for obtaining an input signal value of n bit length for each sampling period, and a value corresponding to a difference value of the input signal value between samplings, a first storage value, and a correction value. a first calculation means for obtaining an n-bit first digital value representing an arithmetic composite value; an output means for outputting an output signal value corresponding to the first digital value;
a first updating means for making a digital value of the first stored value a new first stored value; a second arithmetic means for obtaining a digital value;
The digital value of is effectively (Q-1) bits (here, Q
is an integer such that l<Q<n), and obtains the correction value of n via length to be used in the first calculation means at the next sampling time or a subsequent sampling time. and the (Q
-1) Match the contents of the lower (Q-1) bits up to the 0th bit with the contents of the lower (Q-1> bit) of the digital value in previous writing 2, and match the contents of the lower (Q-1) bits up to the 0th bit
-Q+1) bits to obtain a third digital value having an n-bit length by setting each bit value to the same value as the sign bit of the second digital value; The above-mentioned problem is solved by using a digital filter device that is equipped with a second updating means for setting a second stored value.

Operation In the present invention, with the above configuration, the stored signal value is stored separately into the first stored value and the second stored value, so the actual bit length of the stored signal value is longer than n bits. This results in no bit loss or very little bit loss. As a result, the accuracy of filter calculations is improved. In addition, since the first stored value and the second stored value are each signed digital values, it is easy to add or subtract the correction ([) to the first stored value. In particular, since the correction value is calculated in advance at or before one sampling point, the calculation time from input to output at the next sampling point can be significantly shortened.

Embodiment An embodiment of the digital filter device of the present invention will be described below with reference to the drawings.

FIG. 2 shows a basic configuration diagram of the hardware of the digital filter device of the present invention.
Perform calculations and processes sequentially according to instructions stored in
The instruction storage unit 24 is a ROM (ROM: Read On
ly Memory), and stores the calculation processing algorithm of the digital filter. The input section 21 samples an input signal such as a detection signal of a control device, converts it into a 16-bit digital value, and inputs it to the central processing section 23 . In the central processing unit 23, RAM (RAM:
Filter calculation and processing are performed using the information storage unit 25 configured by Random Access Memory (Random Access Memory), and the calculation results are sent to the output unit 22. Output section 22
The output signal value sent to is used as the control 'f5 signal of the control device. Such an input section 21. output section 22,
Central processing unit 23 (microprocessor).

Instruction storage unit 24. In the digital filter device including the information storage section 25, by appropriately configuring the contents of the instruction storage section 24, it is possible to realize a digital filter having the pulse transfer function G (Zl of the formula +1).

FIG. 1 shows an operation flowchart of the digital filter device of the present invention for realizing the digital filter of formula (1). In the following explanation, the number of processing bits of the central processing unit 23 and the information storage unit 25 is 16 bits, (1)
The coefficient of the equation is 24.

In addition, X, R, U, W, and E in Figure 1 are each 16-bit long (n-16) digital values, the most significant bit is the sign bit, and negative numbers are expressed by two's complement. It is assumed that there is

(l) <Block 1; Input block> The input signal value X1 is input from the input section 21 as a 16-bit digital value.

(2) <Block 2: First calculation block> The difference value (X, -X, .) of the input signal value between sampling periods and the first storage value Wl stored in the information storage unit 25 (described later) A first digital value U1 obtained by arithmetic addition of and a correction value E (described later)
get.

(3) <Block 3: Output Block> The first digital value U1 is output to the output section 22 as the output signal value of the digital filter.

(4) <Block 4: First update block> The information storage unit 2 uses the first digital value U1 as the new first stored value W1.
Update and save to 5.

(5) <Block 5: Second calculation block> Calculate the digital value R1 by arithmetic right-shifting the input signal value x1 by 1 bit.Next, the second storage value W2 stored in the information storage section 25 ( (described later) and the digital value R1, and the second
Obtain the digital value U2.

(6) <Block 6: Correction value calculation block> The second digital value U2 is arithmetic shifted to the right by 3 bits to obtain the correction value E. This correction value E is applied to block 2 at the next sampling point.
(first calculation block). That is, the correction value E to be used at the next sampling time is calculated in advance.

(7) <Block 7: Third calculation block> Logical product (AND) of second digital value U2 and hexadecimal value 8000H
and create a digital value R2. Digital value R2 is 12
Obtain the digital value R3 which is arithmetic shifted to the right by a bit. As a result, in the digital value R3, each bit value of the lower 3 bits from the least significant bit (1st bit) to the 3rd bit is O8 from the 4th bit to the most significant bit (16th bit).
Each bit value of the upper 13 bits up to is equal to the value of the sign bit of the second digital value U2. Then, the logical product (AND) of the second digital value U2 and the hexadecimal value 0007H.
and create a digital value R4. Furthermore, the digital value R
4 and the digital value R3 to obtain the third digital value U3. As a result, the content of the lower 3 bits from the least significant bit to the 3rd bit of the third digital value U3 matches the content of the lower 3 bits of the second digital value U2, and the content of the lower 3 bits of the third digital value U3 matches the content of the lower 3 bits of the second digital value U2. Each bit value of the upper 13 bits from the fourth bit to the most significant bit becomes the same value as the sign bit of the second digital value U2.

(8) <Block 8: Second update block> The information storage unit 2 uses the third digital value U3 as the new second stored value W2.
Update and save to 5.

(9) <Block 9: Input storage block> Input signal value X
, is transferred to Xl-1 and stored.

(1) <Block 10: Delay block> After delaying until the next sampling point, the operation returns to operation (1) of block l.

In this embodiment configured in this manner, the stored signal value is updated and stored using the first stored value W1 and the second stored value W2. In particular, the first stored value W1 and the second stored value W2 each independently have a sign bit, and the least significant bit of the first stored value W1 is numerically the fourth-order bit (Q-4) of the second stored value W2. ). Therefore, the number of bits of the stored signal value is substantially 3 bits [(Q-1) bits] longer than 16 bits (n-16). This improves the accuracy of filter calculations using the input signal values X1 and Xl-1, and eliminates or significantly reduces bit loss. Note that the stored numerical value of the second stored value W2 is limited to a numerical value that can be expressed by the lower 3 bits [(Q-1) bits],
For numerical values larger than this, the correction value E is transferred to the first saved value W1, and the first saved value W1 and the second saved value
The stored values W2 complement each other to represent the stored signal value.

In addition, the calculation process from inputting the new input signal value Xl to obtaining the new output signal value U1 (block 1 to block 3) does not use any comparison calculations or conditional branching. Therefore, the calculation time during this period is is a very small constant value. In particular, since the correction value E to the first stored value Wl resulting from the arithmetic synthesis operation of the second stored value W2 and the input signal value is calculated in advance one sampling point in time, when a new input signal value XI is obtained, The output signal value U1 can be calculated immediately. As a result, the calculation time from input to output becomes extremely short. As a result, when the digital filter device of this embodiment is used as a PI control filter of a control device, a filter with small control time delay can be realized.

Generally, a digital filter performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value, the digital filter having a length of at least n bits. (Here, n is 4
The first stored value and the second stored value each have a sign via), and the least significant bit of the first stored value is Numerically, the 0th bit of the second stored value (where Q is 1<Q<n
(an integer), and the correction value to the first stored value obtained by arithmetic synthesis of the second stored value and the input signal value is set to the input signal value at or before one sampling point. The above effect can be obtained by configuring the system to be calculated in advance using .

Such a configuration and effect are very useful when a general recursive digital filter is used as a control filter for a control device.

In addition, in the above-mentioned embodiment in which the pulse transfer function G (Zl) of equation (1) is realized, if the calculation of R1 in block 5 is changed appropriately, if the coefficient k of equation (1) is not a negative integer power of 2, Moreover, if it is believed that X, +W2 will hardly cause overflow, it is also possible to make R1 equal to Xl.

−a, an input means for obtaining an input signal value of n bit length for each sampling period, and n representing an arithmetic composite value of a value corresponding to the difference value of the input signal value between samplings, a first stored value, and a correction value. a first calculation means for obtaining a first digital value of a bit length; an output means for outputting an output signal value corresponding to the first digital value; and a first calculation means for outputting an output signal value corresponding to the first digital value; a first updating means for performing an arithmetic synthesis operation on a value corresponding to the input signal value at or before the present time and a second stored value to obtain a second digital value having an n-bit length; , the second digital value is substantially (Q-1) bits (where Q is an integer such that 1<Q<n)
arithmetic right-shifting of n bits to obtain the n-bit correction value to be used in the first calculation means at the next sampling time or a subsequent sampling time; 1) Match the contents of the lower (Q-1) bits up to the digit bit with the contents of the lower (Q-1) bit of the second digital value, and Q+1) bits each having the same value as the sign bit of the second digital value to obtain a third digital value having an n-bit length; By configuring a digital filter equipped with a second update means for storing 2 values, a digital filter having the same or almost the same filter characteristics as the pulse transfer function GIZI of equation (1) can be realized with high precision. In addition, the calculation time from human power to output is extremely short.

Note that the information storage section 25 in the above-described embodiment uses a register or a RAM memory whose storage contents can be rewritten. Further, the sampling period may be determined using the detection signal of the control device, etc., which is, of course, included in the present invention, and various other modifications are possible without changing the gist of the present invention.

Effects of the Invention The digital filter device of the present invention is computationally efficient and requires extremely short calculation time from input to output.

Therefore, if a digital filter device that realizes a PI control filter of a control device is constructed based on the present invention, a high-performance control device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the operation of the digital filter of the present invention, FIG. 2 is a basic configuration diagram of the hardware of the digital filter of the present invention, FIG. 3 is a frequency characteristic diagram of the digital filter, and FIG. 4 is a diagram of the frequency characteristics of the digital filter. It is a basic flowchart figure. 21...Input section, 22...Output section, 2
3...Central processing unit, 24...Instruction storage unit, 25...Information storage unit. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Ichiro Kazu (H1')

Claims (3)

[Claims] (1) A digital filter that performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value, the digital filter having at least n bits of the stored signal value. It is stored separately as a first storage value and a second storage value of length (where n is an integer of 4 or more),
The first stored value and the second stored value each have a sign bit, and the least significant bit of the first stored value is numerically the Q-th bit of the second stored value (where Q is 1< Q < n integer), and the correction value to the first stored value obtained by arithmetic synthesis of the second stored value and the input signal value is set at one sampling point or earlier. A digital filter that calculates in advance using the input signal value. (2) According to claim (1), each bit value from the Q-th bit to the most significant bit of the second saved value is made equal to the value of the sign bit of the second saved value. The digital filter device described. (3) Input means for obtaining an input signal value of n bit length for each sampling period, and n bits representing an arithmetic composite value of a value corresponding to a difference value of the input signal value between samplings, a first stored value, and a correction value. a first calculation means for obtaining a first digital value of the length; an output means for outputting an output signal value corresponding to the first digital value; and setting the first digital value as a new first storage value. a first updating means; a second calculating means for performing an arithmetic synthesis operation on a value corresponding to the input signal value at or before the present time and a second stored value to obtain a second digital value having an n-bit length; The second digital value is substantially (
Q-1) arithmetic right shift of bits (here, Q is an integer such that 1<Q<n), and an n-bit length to be used in the first calculation means at the next sampling time or a subsequent sampling time. a correction value calculation means for obtaining the correction value; a third digital value of n-bit length, in which each bit value of the upper (n-Q+1) bits from the most significant bit to the Q-th bit is set to the same value as the sign bit of the second digital value; and a second updating means for making the third digital value the new second stored value.