JPS6379410A - Digital filter device - Google Patents

Abstract

PURPOSE:To attain high performance by summing up an input signal and a stored value signal to form a new stored value signal, dividing the stored value into 1st and 2nd storage values and making the least significant bit of the 1st storage value to a Q-bit of the 2nd storage value. CONSTITUTION:A CPU 23 applies calculation processing sequentially according to an instruction stored in an instruction storage section 24 comprising a ROM. The instruction storage section 24 stores the calculation processing algorithm of the digital filter. An input section 21 samples an input signal and stores it into an information storage section 25 comprising a RAM while being divided into the 1st and 2nd storage values. The CPU 23 uses the data of the RAM 25, the least significant bit of the 1st storage value is made corresponding to the Q-bit of the 2nd storage value to apply the filter calculation/processing and the result is outputted (22). An input section 21, an output section 22, the CPU 23, the instruction storage section 24 and the information storage section 25 constitute the contents of the instruction storage section properly thereby forming the digital filter. Thus, the device with a short arithmetic time and high performance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a recursive digital filter having required filter characteristics, and in particular to a digital filter with good calculation accuracy and short calculation time from input to output. The present invention provides a filter device.

Prior Art In recent years, using microprocessors in control devices,
PI control filters have come to be configured digitally. Here, P means proportional action and ■ means integral action. As such a digital filter for PI control, a recursive digital filter can be used. for example,
A PI control filter having a pulse transfer function G fZl shown in equation (1) below exhibits integral characteristics in a low frequency region, and is suitable for improving the characteristics of a control device. (Not publicly known).

1-(1-k) z.1 -2l Here, zl represents a delay of one sampling time, and k is a constant value coefficient. Figure 3 shows the frequency characteristic near the broken line of the digital filter of formula 11, the corner frequency f in Figure 3.In the following low frequency region, the gain [absolute value of G fil] is -6dB10ct frequency characteristic. The gain becomes larger as the frequency becomes lower.In the frequency range above the corner frequency f, the gain becomes a proportional characteristic with a constant value (approximately OdB).

The coefficients of equation (1) include the sampling time and the corner frequency f in FIG. It is a constant determined by In a PI control filter used in a control device, the coefficient has a value sufficiently smaller than 1. For example, sampling time Ts = 1 (msec), corner frequency f c
= 10 (Ilz), k=24=0.062
It becomes 5.

Next, a method of calculating the PI control filter of equation (1) will be explained with reference to the flowchart of FIG. Fourth
In the figure, x+ and y+ are the new input signal value and the stored signal value, respectively, and x and 1° yl-1 are the input signal value and the stored signal value, respectively, one sampling time before. Note that each signal value is assumed to be a real number 1 or an infinitely long digital value.

(31) <Fronk 31> To sample the new input signal value x1 (32)
<Block 32> Calculate a new stored signal value y1 using the following equation.

yi −)'l-1,000xi ”l-10kxt-1・
...(2) (33) <Block 33> Output the stored signal value yl.

(34) <Block 34> Let Xl and yl be xl-1 and yl-1, respectively.

(35) <Block 35> After a delay until the next sampling point, the operation moves to (31).

By repeating the above operations (31) to (35) and calculating, the characteristics of the PI control filter of formula (11) can be accurately realized.

Problems to be Solved by the Invention However, in reality, the digital values that can be processed by a microprocessor have a finite bit length and can only perform calculations with finite precision. Therefore, a truncation error occurs, which deteriorates the characteristics of the digital filter and adversely affects the control device. In particular, PI of the above formula (1)
Since the filter for control 8 has integral characteristics, the effects of truncation errors appear cumulatively. Regarding this, 16
A case will be described in which a bit-length microprocessor is used to execute the flowchart in FIG. however,
Here, k = 2'.

First, as the first method, y
, and yl-1 may be stored and calculated using one-word digital values each having a length of 16 bits. Here, it is assumed that in a 16-bit digital value, the most significant bit is a sign bit, and negative numbers are expressed by two's complement. That is, if a 16-bit digital value is considered an integer, a numerical value from -32768 to 32767 can be expressed. At this time, k x 1− + in equation (2)
can be calculated using arithmetic right shift. Here, an arithmetic shift of 1 bit to the right substantially corresponds to a doubling.

Therefore, when k ``' 2 '', a 4-bit arithmetic right shift is performed. However, since xl-1 and k Bit loss of information (a phenomenon in which lower bit values are lost) occurs.This greatly reduces the calculation accuracy of equation (2).Especially, since the PI control filter is an integral type filter, this phenomenon occurs. The effects of bit loss accumulate and the filter accuracy deteriorates significantly.As a result, when used in a control device, control performance deteriorates.

In order to prevent such deterioration in calculation accuracy, a second method is to use two words of 16 bits to effectively calculate 3
It is conceivable to express yl and Vi-1 as 2-bit digital values and perform the calculation of equation (2). However, in such a case, calculations involving both the upper and lower words occur, making the calculations extremely complicated. For example, when a carry or a down is caused from the lower word to the upper word, there are four types of 32-bit digital value: a positive number carry, a positive number down, a negative number carry, and a negative number down. It becomes necessary to determine which of the cases is the case. This determination requires many comparative calculations and conditional branches. As a result, the disadvantage is that the calculation time becomes very long. The calculation time from the input to the output of this PI control filter corresponds to the control time delay of the control device. When the control time delay becomes large, the control gain must be reduced in order to ensure the stability of the entire control device. Therefore, the calculation time of the PI control filter is required to be as short as possible.

The present invention takes these points into consideration and provides a digital filter that shortens the calculation time from input to output while improving calculation accuracy.

Means for Solving the Problems The present invention provides a digital filter that performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value. , the stored signal value is at least n bits long (where n
is an integer of 4 or more), and the first and second storage values each have a sign bit, and the first storage value and the second storage value each have a sign bit, and The above problem is solved by configuring the lower bit to numerically correspond to the 0th bit of the second stored value (here, Q is an integer satisfying l<Q<n). .

A more specific configuration of the present invention includes an input means for obtaining an input signal value of n bit length for each sampling period, and a value corresponding to the input signal value at or before one sampling point and a second stored value. a first arithmetic means for performing an arithmetic operation to obtain a first digital value having a length of n bits;
a second arithmetic means for obtaining a second digital value having a bit length by performing an arithmetic right shift of <n integer), a value corresponding to a difference value of the input signal value between samplings, a first storage value, and the second digital value; a third calculation means for obtaining an n-bit third digital value representing an arithmetic composite value of two digital values; and an output means for outputting an output signal value corresponding to the third digital value;
a first updating means for setting the third digital value as a new first stored value; Match the contents of the lower (Q-1) bits of the digital value, and set each bit value of the upper (n-Q+1) bits from the most significant bit to the 0th bit to the same value as the sign bit of the first digital value. and a second updating means for making the fourth digital value the new second stored value. , which solves the above problems.

Operation In the present invention, with the above configuration, the stored signal value is stored separately into the first stored value and the second stored value, so the actual bit length of the stored signal value is longer than n bits. (via) will disappear or will become very small. As a result, the accuracy of filter calculations is improved. In addition, since the first stored value and the second stored value are each signed digital values, it is easy to add or subtract numbers higher than the 0th bit of the second stored value to the first stored value. The calculation time until output can be shortened.

Embodiment An embodiment of the digital filter device of the present invention will be described below with reference to the drawings.

FIG. 2 shows a basic configuration diagram of the hardware of the digital filter device of the present invention. The central processing unit 23 has an instruction storage unit 24
Calculations and processing are performed sequentially according to the instructions stored in the .

The instruction storage unit 24 is a ROM (ROM: Read On
ly Memory), and stores the calculation processing algorithm of the digital filter. The input section 21 samples an input signal such as a detection signal of a control device, converts it into a 16-bit digital value, and inputs it to the central processing section 23 . In the central processing unit 23, RAM (RAM:
Random access memory) is used to perform filter calculations and
The processing is performed and the calculation results are sent to the output section 22. The output signal value sent to the output section 22 is used as a control signal of the control device.
, central processing unit 23 (microprocessor).

Instruction storage unit 24. In the digital filter device including the information storage section 25, by appropriately configuring the contents of the instruction storage section 24, it is possible to realize a digital filter having the pulse transfer function G(Zl) of equation (1).

FIG. 1 shows an operation flowchart of the digital filter device of the present invention for realizing the digital filter of formula (1). In the following explanation, it is assumed that the number of processing bits of the central processing unit 23 and the information storage unit 25 is 16 bits, and (1+
The coefficient of the equation is -24.

In addition, X, R, U, and W in Figure 1 are each 16-bisoto length (n-16) digital values, and the most significant focus is the sign bit, and negative numbers are expressed as two's complement numbers. It is assumed that

(1) <Block 1: Input block> The input signal value x 1 is input from the input section 21 as a 16-bit digital value.

(2) <Block 2: First calculation block> A digital value R1 is calculated by arithmetic right-shifting the input signal value X1-1 one sampling point ago by 1 bit. Next, #l flu
The second storage value W2 (described later) stored in the storage unit 25 and the digital value R1 are added by 'M, 447 to obtain the first digital value Ul.

(3) <Flock 3: Second calculation block> 1st
A second digital value U2 is obtained by performing a 3-bit arithmetic right shift on the digital value tJ1.

(4) <Block 4: Third calculation block> Difference value (X, -X,,) of input signal values between sampling periods and first storage value Wl stored in the information storage unit 25 (described later) and the second digital value U2 are calculated (and the third digital value U3 is obtained by adding the tochi.

(5) <Block 5: Output Block> Outputs the third digital signal (i3) to the output section 22 as the output signal value of the digital filter.

f61 <Flock 6: First update block> The third digital value U3 is updated and stored in the information storage unit 25 as a new first storage value W1.

(7) <Block 7: Fourth calculation block> Logical product (AND) of the first digital value U1 and hexadecimal value 8000H
and create a digital value R2. Digital (!R2 to 1
Obtain digital ray direct R3 which is arithmetic shifted to the right by 2 bits.

As a result, in the digital value R3, each bit value of the lower three pinpoints from the least significant bit (first bit) to the third bit is 0. Each bit value of the upper 13 bits from the 4th bit to the most significant bit (16th bit) becomes equal to the value of the sign bit of the first digital value U1. Next, the first
The logical product of the digital value U1 and the hexadecimal value 0007H (A
ND) and create a digital value R4. Furthermore, calculate the logical sum (OR>) of the digital value R4 and the digital value R3,
A fourth digital value U4 is obtained. As a result, the contents of the lower 3 bits from the least significant bit to the 3rd bit of the fourth digital value U4 match the contents of the lower 3 bits of the first digital value Ul, and the contents of the lower 3 bits of the fourth digital value U4 match. Each of the 13 higher order focus values from the 4th bit to the most significant bit has the same value as the sign bit of the first digital value U1.

(8) <Block 8: Second update block> The information storage unit 2 uses the fourth digital value U4 as the new second stored value W2.
Update and save to 5.

(9) <Block 9: Input storage block> Input signal value X
1 to X+-+ and save.

QOl<Block 10: Delay block> After delaying until the next sampling point, the operation returns to block 1+11.

In this embodiment configured in this manner, the stored signal value is updated and stored using the first stored value W1 and the second stored value W2. In particular, the first stored value W1 and the second stored value W2 each independently have a sign bit, and the least significant bit of the first stored value W1 is numerically the fourth-order bit (Q
=, t). Therefore, the number of bits of the stored signal value is substantially 3 bits [(Q-1) bits] longer than 16 bis 1- (n=16). As a result, the input signal value X! The accuracy of filter calculations using Xl-3 and Xl-3 is improved, and bit loss can be eliminated or significantly reduced. Note that the stored numerical value of the second stored value W2 is limited to a value that can be expressed by the lower 3 bits [(Q-1) bits], and larger numerical values are moved to the first stored value W1, The first stored value W1 and the second stored value w2 complement each other to represent the stored signal value.

In addition, no comparison calculation or conditional branching is used in the arithmetic processing from when the new input signal value X1 is input to when the new output signal value U3 is obtained (block 1 to block 5). Therefore, the computation time during this period is a very small constant value. As a result, when the digital filter device of this embodiment is used as a PI control filter of a control device, a filter with small control time delay can be realized.

Generally, a digital filter performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value, the digital filter having a length of at least n bits. (Here, n is 4
(integer greater than or equal to)) is stored separately into a first stored value and a second stored value, and the first stored value and the second stored value each have a sign bit, and the least significant bit of the first stored value is numerically the 0th-order bit of the second stored value (here, Q is 1<
If the configuration is configured to correspond to Q<n (an integer), the above effect can be obtained. Such a configuration and effect are very useful when a general recursive digital filter is used as a control filter for a control device.

In addition, in the above-mentioned embodiment in which the pulse transfer function G (Zl) of equation (1) is realized, if the calculation of R1 in block 2 is changed appropriately, it can be realized even when the coefficient k of the fi1 equation is not a negative integer power of 2. Yes, it is possible. Furthermore, if Xl-+"W2 is expected to cause little overflow, it is also possible to make R1 equal to Xl-1.

In general, an input means for obtaining an n-bit long input signal value for each sampling period, and an arithmetic operation on a value corresponding to the input signal value at or before one sampling point and a second stored value to obtain an n-bit long input signal value. a first calculation means for obtaining a first digital value; and a first calculation means for obtaining a first digital value;
) bits (where Q is an integer such that l<Q<fi) to obtain a second digital value of length n bits, which is arithmetic right-shifted.
a third digital value having an n-bit length representing an arithmetic composite value of a value corresponding to a difference value of the input signal value between samplings, a first stored value, and the second digital value; a calculation means for outputting an output signal value corresponding to the third digital value; a first updating means for making the third digital value the new first storage value; The lower order bit (Q-1) up to the (Q-1)th bit
) bit contents of the first digital value (Q-1
) bits, and each bit value of the upper (n-Q+1) bits from the most significant bit to the 0th bit is set to the same value as the sign bit of the first digital value. If a digital filter device is constructed, which includes a fourth calculating means for obtaining a digital value, and a second updating means for making the fourth digital value the new second stored value, the pulse of the formula (]) A digital filter having the same or almost the same filter characteristics as the transfer function G tz+ can be realized with high precision. Furthermore, the calculation time from input to output is also shortened.

Note that the information storage section 25 in the above-described embodiment uses a register or a RAM memory whose storage contents can be rewritten. Further, the sampling period may be determined using the detection signal of the control device, etc., and it goes without saying that this is included in the present invention. In addition, various modifications can be made without changing the spirit of the present invention.

Effects of the Invention The digital filter device of the present invention has good calculation accuracy and short calculation time from input to output. Therefore, if a digital filter device that realizes a PI control filter of a control device is constructed based on the present invention, a high-performance control device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the operation of the digital filter of the present invention, FIG. 2 is a basic configuration diagram of the hardware of the digital filter of the present invention, FIG. 3 is a frequency characteristic diagram of the digital filter, and FIG. 4 is a diagram of the frequency characteristics of the digital filter. It is a basic flowchart figure. 21...Human power section, 22...Output section, 2
3...Central processing unit, 24...Instruction storage unit, 25...Information storage unit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 Figure 3

Claims (3)

[Claims] (1) A digital filter that performs an arithmetic synthesis operation on at least one input signal value and at least one stored signal value, and uses the result of the calculation as a new stored signal value, the digital filter having at least n bits of the stored signal value. It is stored separately as a first storage value and a second storage value of length (where n is an integer of 4 or more),
The first stored value and the second stored value each have a sign bit, and the least significant bit of the first stored value is numerically equal to the Q-order bit of the second stored value (where Q is 1<Q
<An integer n). (2) According to claim (1), each bit value from the Q-th bit to the most significant bit of the second saved value is made equal to the value of the sign bit of the second saved value. The digital filter device described. (3) an input means for obtaining an n-bit long input signal value for each sampling period; and an n-bit length for performing an arithmetic operation on a value corresponding to the input signal value at or before one sampling point and a second stored value. a first calculation means for obtaining a first digital value of (Q-1);
a second arithmetic means for obtaining a second digital value having a length of n bits, which is arithmetic right-shifted by bits (here, Q is an integer satisfying 1<Q<n); and a second calculation means corresponding to a difference value of the input signal value between samplings. a third digital value of n bit length representing an arithmetic composite value of the stored value, the first stored value, and the second digital value;
a calculation means for outputting an output signal value corresponding to the third digital value; a first updating means for making the third digital value the new first storage value; The contents of the lower (Q-1) bits up to the (Q-1)th bit are made to match the contents of the lower (Q-1) bits of the first digital value, and the contents of the lower (Q-1) bits from the most significant bit to the Q-th bit are a fourth arithmetic means for obtaining a fourth digital value having an n-bit length by setting each bit value of the upper (n-Q+1) bits to the same value as the sign bit of the first digital value;
a digital filter device comprising second updating means for setting the digital value of , as the new second stored value.