JPS63245518A - Dividing arithmetic unit - Google Patents

Abstract

PURPOSE:To eliminate excess operations and to increase the operation speed by discriminating whether overflow occurs or not in the end of dividing operation. CONSTITUTION:After division is repeated a prescribed number of times to obtain a quotient, contents of an overflow instructing circuit 7 are checked. The one-bit flag held in the circuit 7 indicates whether the first operation result in an ALU 4 is negative or not. One bit outputted from a division result generat ing circuit 5 at the time of terminating a first operation in the ALU 4 is finally shifted to the circuit 7 by a prescribed number of shift operations in a register 2 and reflects on this flag as the result. Consequently, when the flag is '1', A>=B is satisfied at the first time and final data C obtained in the register 2 is not a correct quotient, and the overflow processing is performed. When the flag of the circuit 7 is '0', data C is a correct quotient.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a division arithmetic device, and more particularly to a division arithmetic device that calculates a quotient by repeating subtraction and shift operations.

(Prior art) A division arithmetic device has a register for storing the dividend, a register for storing the divisor, and a register for storing the quotient. Generally, a part of the register for storing the dividend is also used as a register for storing the quotient. is being carried out. Division is performed by repeatedly subtracting the divisor from the higher digits of the dividend, shifting the dividend to the left after one subtraction, and performing the next subtraction. The quotient is obtained by arranging the signs of each subtraction result as 1 and 0.

If the dividend is larger than the divisor, the quotient obtained as a result of the division will also be larger, resulting in a situation where there are not enough digits in the register to store the quotient. In other words, the division will overflow, making it impossible to obtain a correct operation result. For this reason, in conventional division arithmetic devices, before performing an actual division operation, a comparison operation is performed to compare the dividend and the divisor to determine whether an overflow occurs.

(Problems to be Solved by the Invention) As mentioned above, in the conventional division operation device, before every division operation, a comparison operation is performed to check whether there is an overflow, which takes extra time. A problem has arisen in that the calculation speed becomes slow.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a division arithmetic device that does not require extra arithmetic operations and has high arithmetic speed.

[Structure of the invention]

(Means for Solving the Problems) The present invention has a first register for storing the high-order digits of the dividend, a second register for storing the low-order digits of the dividend, and a third register for storing the divisor. A register, an ALU that performs subtraction or addition between the contents of the first register and the contents of the third register, a division result generation circuit that indicates that the operation result of this ALU is negative, and this division result A that causes the ALU to perform addition only when the generation circuit indicates a negative value.
After the ALU completes one operation, the operation result is shifted to the left by 1 bit and placed in the first register, and the contents of the second register are shifted to the left by 1 bit. and puts its most significant bit into the least significant bit of the first register, and when the division result generation circuit indicates a negative value, it is set to “0”.
In other cases, 21'' is placed in the least significant bit of the second register to perform the next operation, and the operation is continued as many times as necessary until the quotient is obtained in the register in Section 2 below. In the division arithmetic unit, the bit shifted from the most significant bit of the second register after the completion of the required number of operations is held, and when this bit is “1”, it indicates that the division is an overflow. An overflow indicating circuit is further provided.

(Function) In the division arithmetic device according to the present invention, it is determined whether there is an overflow or not based on the bit shifted from the most significant bit of the second register after the required number of operations are completed. That is, when this bit is "1", it is indicated that the division is an overflow. This bit is generated by the division result generation circuit based on the operation result when the first subtraction is performed, and the fact that this bit is "1" indicates that the result of the first subtraction was positive.

That is, it indicates that the contents of the first register are initially greater than or equal to the contents of the third register. In this way, since it is possible to determine whether there is an overflow at the end of the division operation, there is no need to perform a comparison operation before the division operation, unlike in conventional division operation devices, which eliminates unnecessary operations and speeds up the operation. can be improved.

(Example) The present invention will be described below based on an illustrative example. The division arithmetic device according to the present invention is characterized in that an overflow instruction circuit is newly provided in the conventional division arithmetic device. Therefore, for convenience of explanation, first, the configuration and operation of a conventional division arithmetic device will be described for reference.

FIG. 3 is a block diagram showing an example of a conventional division arithmetic device. This device has three registers: a first register 1, a second register 2, and a third register 3. Each register can hold, for example, 8 bits of data. The upper digits of the dividend are placed in the first register 1, and the lower digits are placed in the second register 2. Also, the divisor is placed in the third register 3. The quotient resulting from the division operation is finally obtained in the second register 2. Therefore, in this example, it is possible to divide a dividend of up to 16 bits by a divisor of up to 8 bits, and if the resulting quotient exceeds 8 bits, an overflow occurs. below,
To simplify the explanation, the contents of the first register 1, second register 2, and third register 3 will be referred to as data A1 data B1 data C, respectively.

ALU4 is a circuit that performs various operations between data A and data B. Here, in addition to subtraction and addition of both data, a comparison operation is performed. The results of the subtraction and addition are returned to the first register 1 again. At this time, as will be described later, the data is shifted to the left by one bit and then returned.

The division result generation circuit 5 outputs o" or "1" depending on the operation performed by the ALU 4. That is, when the operation result is negative, "0" is output, and otherwise, "1" is output.
Each is output. This output goes into the least significant bit of the second register 2. Note that at this time, the second register 2
The data C that was in the register is shifted one bit to the left, and the most significant bit of the data C is placed in the least significant bit of the first register 1.

The ALU function selection circuit 6 is a circuit that specifies whether the operation to be performed by the ALU 4 during a division operation is subtraction or addition. When "0" is given from the division result generation circuit 5, the ALU function selection circuit 6 specifies the next operation of the ALU 4 to be addition. And given s 1 ++, A
It has a function to specify the next operation of LU4 as subtraction.

The division procedure performed by this device will be explained with reference to the flowchart shown in FIG. First, in step s1, a divisor is set as data B in the register 3. Subsequently, in step S2, the upper digits of the dividend are set as data A in register 1, and the lower digits are set as data C in register 2. Then, in step S3, ALU4 is set to comparison operation. As a result, in step S4, data A and data B are compared with each other. Here, if A≧B, overflow processing is performed in step S5 and no division is performed. A≧B means that the higher digits of the dividend are larger than the divisor, so even if division is performed, the number of digits in the quotient will be too large to be stored in the second register 2.

In step S4, the following division will be performed only if A<B. First, in step S6, A
LU4 is set to subtract. Therefore, step S
At 7, a subtraction A-B is performed, and the data obtained as a result of this operation is shifted to the left by one bit and placed in the first register 1. Then, in step S8, data C in the second register 2 is shifted to the left by 1 bit. At this time, the most significant bit of the data C that has come out of the second register 2 will enter the least significant bit of the first register 1. Further, the least significant bit of this second register 2 receives the output of the division result generation circuit 5 in step S9. As mentioned above, the division result generation circuit 5
If the calculation result in LU4 is negative, "0" is generated, and otherwise, "1" is generated. In the end, the bit string generated by the division result generation circuit 5 becomes the quotient. Also,
In step S10, the ALU function selection circuit 6 sets, based on the output of the division result generation circuit 5, whether the next operation to be performed in the ALU 4 is subtraction or addition. When the division result generation circuit 5 outputs "0", addition is set, and when it outputs "1", subtraction is set.

The procedure from steps 87 to S10 described above is repeated a predetermined number of times, that is, the number of bits of the second register 2+1. At this time, the calculation in step S7 is the calculation set in step S10. When the predetermined number of repetitions are completed in this manner, all division procedures are completed through step S11. The quotient to be determined is obtained in the second register 2.

On the other hand, a block diagram of an embodiment of a division arithmetic device according to the present invention is shown in FIG. This device is the conventional device shown in FIG. 3 in which an overflow indicating circuit 7 is further provided. In this embodiment, the overflow instruction circuit 7 indicates the carry flag of the data C in the second register 2.

Therefore, the original most significant bit when data C in the second register 2 is shifted to the left is placed in the most significant bit of the first register 1, and is held as a carry flag in the overflow instruction circuit 7. That will happen.

The division procedure performed by this device is shown in the flowchart of FIG. Step S1 and step s2 are completely similar to the conventional procedure. However, the conventional step S3. The division procedure from step S6 is started without performing step S4. That is, the division procedure is proceeded without checking in advance whether or not there will be an overflow. The iterative procedure for calculating the quotient from steps S6 to S11 is almost the same as the conventional procedure. However, as shown in step S8', in the procedure of shifting the data C, the most significant bit of the data C is put into the least significant bit of the first register 1 and is held in the overflow instruction circuit 7.

When the predetermined number of repetitions are completed in this way, the contents of the overflow instruction circuit 7 are checked in step S12. The 1-bit flag held in the overflow instruction circuit 7 is originally a flag indicating whether the first calculation result in the ALU 4 is negative or not. That is, the 1 bit output from the division result generation circuit 5 at the end of the first operation by the ALU 4 is finally shifted to the overflow instruction circuit 7 by a predetermined number of shift operations in the second register 2. be. Therefore, in step S12, if this flag is determined to be "1", the first A
The result of the calculation by LU4 was not negative, in other words, A≧B at the beginning. Therefore, in this case, since the data C finally obtained in the second register 2 is not a correct value as a quotient, overflow processing is performed in step S5. Conversely, if the flag in the overflow instruction circuit 7 is "0", it means that a correct quotient has been obtained for the data C.

As mentioned above, in the calculation in the conventional division calculation device, step S3. Although the overflow determination step S4 must be performed before the division step, in the division arithmetic device according to the present invention, step S12 is performed after the division step is completed.
At this time, it is only necessary to check the flag in the overflow instruction circuit 7. Therefore, redundant calculations can be omitted and calculation time can be shortened.

〔Effect of the invention〕

As described above, according to the division arithmetic device according to the present invention, the presence or absence of an overflow is determined based on the 1-bit data that has been shifted last from the register where the quotient is finally obtained, so that unnecessary operations can be omitted. It is possible to improve the calculation speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a division arithmetic device according to an embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the device shown in FIG. 1, and FIG. 3 is a block diagram of a conventional division arithmetic device. ,
FIG. 4 is a flowchart for explaining the operation of the apparatus shown in FIG. 3. 1...First register, 2...Second register, 3
...Third register, 4...ALU, 5...Division result generation circuit, 6...ALU function selection circuit, 7...
Overflow instruction circuit, 81-S12...each step of the flowchart. Applicant's agent Mr. Sato Figure 1 Figure 3

Claims (1)

[Claims] 1. A first register for storing high-order digits of the dividend;
a second register for storing lower digits of the dividend;
a third register for storing a divisor; an ALU for subtracting or adding between the contents of the first register and the contents of the third register; and an ALU function selection circuit that causes the ALU to perform addition only when the division result generation circuit indicates a negative value. The operation result is shifted to the left by 1 bit and placed in the first register, and the contents of the second register are shifted to the left by 1 bit, and the most significant bit is placed in the least significant bit of the first register. When the division result generating circuit indicates a negative value, "0" is entered into the least significant bit of the second register, and otherwise "1" is entered into the least significant bit of the second register to perform the next operation. In a division arithmetic device configured to continue an arithmetic operation a necessary number of times until a quotient is obtained in a register, the bits shifted from the most significant bit of the second register after the necessary number of operations are completed. 1. A division arithmetic device further comprising an overflow indicating circuit which holds a bit and indicates that the division is an overflow when this bit is "1". 2. The division arithmetic device according to claim 1, wherein the first register, the second register, and the third register each have the same bit capacity. 3. “0” when the division result generation circuit indicates a negative value
3. The division arithmetic device according to claim 1 or 2, wherein the division arithmetic device outputs "1" at other times. 4. A first register for storing the high-order digits of the dividend;
a second register for storing lower digits of the dividend;
a third register for storing a divisor; an ALU that performs subtraction between the contents of the first register and the third register; and a division unit that indicates that the result of the operation of this ALU is negative. and a result generation circuit, and after the ALU finishes one operation, only when the operation result becomes 0 or positive, shifts the operation result by 1 bit to the left and stores it in the first register. , if the operation result is negative, the contents of the first register are shifted to the left by 1 bit, the contents of the second register are shifted to the left by 1 bit, and the most significant bit thereof is transferred to the first register. When the division result generation circuit indicates a negative value, it is set to “0”, and otherwise, it is set to “1”.
” into the least significant bit of the second register, performs the next operation, and continues the operation as many times as necessary until the quotient is obtained in the second register. , an overflow instruction that holds a bit shifted from the most significant bit of the second register after the completion of the required number of operations, and indicates that the division is an overflow when this bit is "1"; A division arithmetic device further comprising a circuit. 5. Claim 4, wherein the first register, the second register, and the third register each have the same bit capacity. The division arithmetic device described in Section 6. “0” when the division result generation circuit indicates a negative value.
6. The division arithmetic device according to claim 4 or 5, wherein the division arithmetic device outputs "1" at other times.