JPS6378572A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6378572A JPS6378572A JP22092986A JP22092986A JPS6378572A JP S6378572 A JPS6378572 A JP S6378572A JP 22092986 A JP22092986 A JP 22092986A JP 22092986 A JP22092986 A JP 22092986A JP S6378572 A JPS6378572 A JP S6378572A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- drain region
- source region
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ポリシリコントランジスタにおいてソースドレイン間に
薄い酸化膜等の障壁を設けることによって、トランジス
タカットオフ時のソースドレイン間のリーク電流を低下
させる。[Detailed Description of the Invention] [Summary] By providing a barrier such as a thin oxide film between the source and drain of a polysilicon transistor, leakage current between the source and drain at the time of transistor cutoff is reduced.
本発明は半導体装置に係り、特にソースドレイン間に障
壁を設けたポリシリコントランジスタに関するものであ
る。The present invention relates to a semiconductor device, and particularly to a polysilicon transistor in which a barrier is provided between a source and a drain.
多結晶シリコン（Ｐｏｌｙ Ｓｉ） トランジスタは
絶縁膜例えば二酸化珪素（ＳｉＯｚ）上に素子を形成す
ることができる。このＰｏ１ｙ Ｓｉ Ｔｒは三次元デ
バイスとして５ｏｌ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕ
ｌａｔｉｏｎ）に比較して単結晶シリコンを成長させる
必要がないという製造上の容易性から有利である。A polycrystalline silicon (PolySi) transistor can be formed on an insulating film such as silicon dioxide (SiOz). This PolySi Tr is 5ol (Silicon On In5u) as a three-dimensional device.
This method is advantageous in terms of ease of manufacturing as it does not require the growth of single crystal silicon.
第３図は従来のＰｏ１ｙ Ｓｉ トランジスタを示す
概略断面図である。FIG. 3 is a schematic cross-sectional view showing a conventional PolySi transistor.
第３図によればＳｉＯ□層１上に多結晶シリコン層３が
形成され、ソース領域２ａ及びドレイン領域２ｂが設け
である。多結晶シリコン層３上には更にゲート酸化膜４
及びゲート電極５が設けれらている。According to FIG. 3, a polycrystalline silicon layer 3 is formed on a SiO□ layer 1, and a source region 2a and a drain region 2b are provided. Further, a gate oxide film 4 is formed on the polycrystalline silicon layer 3.
and a gate electrode 5 are provided.
従来このようなＰｏ１ｙ Ｓｉ Ｉ・ランジスタのカ
ットオフ時でも、ソース領域２ａとトレイン領域２ｂと
の間が多結晶シリコンであるために著かではあるがリー
ク電流が流れる。このリーク電流のため従来Ｐｏ１ｙＳ
ｉ）ランジスタはトランジスタとして実用化が困５Ｍで
あった。Even during cutoff of such a conventional Po1ySiI transistor, a leakage current flows, albeit considerably, because the region between the source region 2a and the train region 2b is made of polycrystalline silicon. Due to this leakage current, conventional Po1yS
i) It was difficult to put the transistor into practical use as a transistor.
本発明は多結晶シリコントランジスタにおいて、ソース
・ドレイン領域間のリーク電流を低下させることを目ｎ
勺とする。The present invention aims to reduce leakage current between the source and drain regions in polycrystalline silicon transistors.
I'm going to do it.
上記問題点は本発明によれば半４体基板上に形成された
二酸化シリコン層上に形成された多結晶シリコン層から
なるソース領域とドレイン領域とｉｆ ｊＸ多結晶シリ
コン上に形成されたゲート電極を具備する半導体装置に
おいて、前記ソース領域とドレイン領域間にトンネル障
壁層を設けることを特徴とする半導体装置によって解決
される。According to the present invention, the above-mentioned problem can be solved by forming a source region and a drain region made of a polycrystalline silicon layer formed on a silicon dioxide layer formed on a semi-quartet substrate, and a gate electrode formed on an if jX polycrystalline silicon layer. The present invention is solved by a semiconductor device comprising: a tunnel barrier layer provided between the source region and the drain region.
本発明によればソース領域とドレイン領域間に設けられ
た薄い厚さの絶縁層によって上記二つの領域間に流れる
リーク電流を防止することが可能となる。According to the present invention, the thin insulating layer provided between the source region and the drain region makes it possible to prevent leakage current from flowing between the two regions.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１Ａ図及び第１Ｂ図は本発明の詳細な説明するための
模式断面図である。FIG. 1A and FIG. 1B are schematic cross-sectional views for explaining the present invention in detail.
第１Ａ図及び第１Ｂ図において１はＳｉＯ２層、２ａは
ソース領域、２ｂはドレイン領域、３は多結晶シリコン
層、４はＳｉＯ□からなるゲート酸化膜、５はゲート電
極であり１０が本発明に係る障壁層（トンネル酸化膜薄
いＳｉ３Ｎ、膜等）である。In FIGS. 1A and 1B, 1 is a SiO2 layer, 2a is a source region, 2b is a drain region, 3 is a polycrystalline silicon layer, 4 is a gate oxide film made of SiO□, 5 is a gate electrode, and 10 is the invention. This is a barrier layer (tunnel oxide film, thin Si3N film, etc.) related to this.
原理同第１Ａ図はソース・ドレイン領域が２つの障壁層
で仕切られているのに対し第１Ｂ図は１つの障壁層で仕
切られている。これらの障壁層の電流方向の厚さはリー
ク電流は流さぬ程度のトンネル効果を有する厚さにする
。The principle is that in FIG. 1A, the source/drain region is partitioned by two barrier layers, whereas in FIG. 1B, it is partitioned by one barrier layer. The thickness of these barrier layers in the current direction is set to a thickness that provides a tunnel effect to the extent that leakage current does not flow.
第２Ａ図から第２Ｇ図は上記第１Ａ図の具体的製造法を
示す工程断面図である。FIGS. 2A to 2G are process cross-sectional views showing a specific manufacturing method shown in FIG. 1A.
第２Ａ図においてＳｉＯ□層１上にＣＶＤ （化学的気
相成長）法によって４０００人のＪ７さに第１の多結晶
シリコン層３を形成し、ゲート電極形成部を除去するよ
うに多結晶シリコン層３をＲＩＥ（反応性イオンエツチ
ング）によりパターニングコンタクトホール６を形成す
る。次に第２Ｂ図に示すように約１００ 人の厚さにト
ンネル障壁層としてＳｉＯ２膜１０ａを形成する。In FIG. 2A, a first polycrystalline silicon layer 3 is formed on the SiO□ layer 1 by the CVD (chemical vapor deposition) method in J7 of 4000 layers, and the polycrystalline silicon layer 3 is formed so as to remove the gate electrode forming portion. Patterning contact holes 6 are formed in the layer 3 by RIE (reactive ion etching). Next, as shown in FIG. 2B, a SiO2 film 10a is formed as a tunnel barrier layer to a thickness of about 100 nm.
次に第２多結晶シリコン層７をＣＶＤ法により約６００
０人の厚さに全面に形成し、次に第２Ｇ図に示すように
ボロンをチャネルドープとしてイオン注入８を行なう。Next, the second polycrystalline silicon layer 7 is deposited with a thickness of approximately 600 nm by CVD.
It is formed over the entire surface to a thickness of 0.0 mm, and then, as shown in FIG. 2G, ion implantation 8 is performed using boron as a channel dope.
次に第２Ｅ図に示すように全面に約３００人の厚さにゲ
ート酸化膜であるＳｉＯ□膜９を熱酸化により形成する
。次に第２Ｆ図に示すように約４０００人の厚さにＣＶ
Ｄ法により第３の多結晶シリコン層１１を全面に形成し
、第２Ｇ図に示すようにゲート電極１４を形成すべく第
３の多結晶シリコン層１１ 、ＳｉＯ□膜９、そして第
２の多結晶シリコン層７、を順次ｔＢ法によりパターニ
ングする。そのパターニングの後５ｉｎ２膜１０ａを介
して砒素をイオン注入しソース領域２ａ及びドレイン領
域２ｂを形成する。Next, as shown in FIG. 2E, a SiO□ film 9, which is a gate oxide film, is formed by thermal oxidation to a thickness of about 300 mm over the entire surface. Next, as shown in Figure 2F, the CV is approximately 4,000 thick.
A third polycrystalline silicon layer 11 is formed on the entire surface by method D, and as shown in FIG. 2G, the third polycrystalline silicon layer 11, the SiO The crystalline silicon layer 7 is sequentially patterned by the tB method. After patterning, arsenic ions are implanted through the 5in2 film 10a to form a source region 2a and a drain region 2b.
このようにして５ｉｏｚＪＦｆ上に、ソース領域２ａ及
びドレイン領域２ｂ上面にそれぞれトンネル障壁層とし
て５ｉＯｚ膜１０ａを有するトランジスタを形成するこ
とができる。この５ｉ０２膜１０ａはリーク電流を阻止
し動作電流のみを流すことができる。In this manner, a transistor can be formed on the 5iOz JFf, having the 5iOz film 10a as a tunnel barrier layer on the upper surfaces of the source region 2a and drain region 2b, respectively. This 5i02 film 10a can block leakage current and allow only operating current to flow.
以上説明したように本発明によればソース領域とドレイ
ン領域間にトンネル障壁層が形成されているのでリーク
電流を防止し多結晶シリコントランジスタ特性を向上さ
せることができる。As described above, according to the present invention, since a tunnel barrier layer is formed between the source region and the drain region, leakage current can be prevented and the characteristics of the polycrystalline silicon transistor can be improved.
第１Ａ図及び第１Ｂ図は本発明の詳細な説明するための
模式断面図であり、第２Ａ図から第２Ｇ図は上記第１Ａ
図の具体的製造法を示す工程断面図であり、第３図は従
来のＰｏ１ｙ Ｓｉ トランジスタを示す概略断面図
である。
１・・・５ｉＯｚ層、 ２ａ・・・ソース領
域、２ｂ・・・ドレイン領域、 ３・・・多結晶シリ
コン層、３ａ・・・第一の多結晶シリコン層、
４・・・ゲート酸化膜（ＳｉＯ□膜）、５・・・ゲート
電極、 ６・・・コンタクトホール、７・・・第
２多結晶シリコン層、
８・・・イオン注入、 ９・・・ＳｉＯ□膜、１０
ａ・・・トンネル障壁層（ＳｉＯ□膜）、１１・・・第
３の多結晶シリコン層、
１４・・・ゲート電極。FIGS. 1A and 1B are schematic sectional views for explaining the present invention in detail, and FIGS. 2A to 2G are schematic cross-sectional views of the above-mentioned
FIG. 3 is a process cross-sectional view showing a specific manufacturing method shown in the figure, and FIG. 3 is a schematic cross-sectional view showing a conventional PolySi transistor. 1... 5iOz layer, 2a... Source region, 2b... Drain region, 3... Polycrystalline silicon layer, 3a... First polycrystalline silicon layer, 4... Gate oxide film ( SiO□ film), 5... Gate electrode, 6... Contact hole, 7... Second polycrystalline silicon layer, 8... Ion implantation, 9... SiO□ film, 10
a... Tunnel barrier layer (SiO□ film), 11... Third polycrystalline silicon layer, 14... Gate electrode.
Claims (1)
成された多結晶シリコン層からなるソース領域とドレイ
ン領域と該該多結晶シリコン上に形成されたゲート電極
を具備する半導体装置において、 前記ソース領域とドレイン領域間にトンネル障壁層を設
けることを特徴とする半導体装置。[Claims] 1. A source region and a drain region made of a polycrystalline silicon layer formed on a silicon dioxide layer formed on a semiconductor substrate, and a gate electrode formed on the polycrystalline silicon layer. A semiconductor device, characterized in that a tunnel barrier layer is provided between the source region and the drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22092986A JPS6378572A (en) | 1986-09-20 | 1986-09-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22092986A JPS6378572A (en) | 1986-09-20 | 1986-09-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6378572A true JPS6378572A (en) | 1988-04-08 |
Family
ID=16758765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22092986A Pending JPS6378572A (en) | 1986-09-20 | 1986-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6378572A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012248896A (en) * | 2007-06-08 | 2012-12-13 | Beijing Boe Optoelectronics Technology Co Ltd | Thin film transistor and manufacturing method thereof |
| US9337255B1 (en) | 2014-11-21 | 2016-05-10 | International Business Machines Corporation | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
-
1986
- 1986-09-20 JP JP22092986A patent/JPS6378572A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012248896A (en) * | 2007-06-08 | 2012-12-13 | Beijing Boe Optoelectronics Technology Co Ltd | Thin film transistor and manufacturing method thereof |
| US9337255B1 (en) | 2014-11-21 | 2016-05-10 | International Business Machines Corporation | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
| US9337309B1 (en) | 2014-11-21 | 2016-05-10 | International Business Machines Corporation | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
| US9564514B2 (en) | 2014-11-21 | 2017-02-07 | International Business Machines Corporation | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels |
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