JPS6376423A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a trench capacitor easily and make a region which is formed on the side surface of a trench and has a conductivity type opposite to the conductivity type of a semiconductor substrate by a method wherein impurity ions are implanted obliquely into the side surface of a recessed part or the protruding part which is selectivity formed on the main surface of the semiconductor substrate. CONSTITUTION:A recessed part 13 or a protruding part is formed on the main surface of semiconductor substrate 11 and impurity ions are implanted into at least one of its side surface obliquely with a predetermined angle theta from line perpendicular to the plane of the substrate 11. For instance, after a silicon oxide film 12 is deposited over the whole surface of a P-type silicon substrate 11, the oxide film 12 is patterned and the substrate 11 is etched by RIE with the patterned oxide film 12 as a mask to form a trench 13. After that, phosphorus ions are implanted from the opening of the trench 13 to form and N-type ion implanted region 14 on the side surfaces and the bottom surface of the trench 13. At that time, the angle theta of ion implantation is so controlled as tp be about + or - 7 degrees from a line perpendicular to the plane of the substrate 11. Then, after the oxide film 12 is removed, a hot oxide film 15 is formed and a polycrystalline silicon layer 16 is deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device having a trench capacitor.

(Prior Art) In a dynamic semiconductor memory device (hereinafter referred to as D-RAM), in order to increase the capacity by reducing the size of each cell, so-called one transistor, one Memory cells having a capacitor configuration are widely used. Among these, the so-called trench capacitor, in which the capacitor is formed on the inner surface of a groove formed in the substrate, can reduce the cell size more than the planar capacitor, so the recent D-
Most RAMs use this type of capacitor.

FIG. 6 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device having such a trench capacitor.

First, for example, CVD is applied to the entire surface of the P-type silicon substrate 21.
Silicon oxidation l1lI2 by (chemical vapor deposition method)
After depositing silicon oxide film 22, this silicon oxide film 22 is patterned by photolithography or the like. Furthermore, using this patterned silicon oxide 1122 as a mask, the silicon substrate 21 is etched by RIE (reactive ion etching technique) to form a trench 23 having a depth of, for example, 4 μm (FIG. 6(a)).

After that, arsenic containing arsenic (As) as an N-type impurity
A silicon glass film (AsSG film) 24 is deposited on the entire surface,
Furthermore, thermal diffusion is performed to form an N+ type diffusion region Ta25 inside the trench 23 (FIG. 6(b)).

Next, the arsenic-silicon glass II used in the above diffusion!
After removing I24 and the silicon oxide II22 used as a patterning mask, a thermally oxidized WA26 is formed to a thickness of, for example, about 150 mm, and a polycrystalline silicon layer 27, which is an electrode material, is deposited thereon. The trench capacitor is completed (FIG. 6(C)).

The trench capacitor formed in this way can be made much finer than the planar capacitor as described above. However, according to the conventional method, an in-phase diffusion technique using arsenic-silicon lath 1124 is used to form a region of the opposite conductivity type to that of the substrate on the side surface of the trench, which complicates the process. There are drawbacks such as a problem in controllability of the surface impurity concentration of the opposite conductivity type region formed on the side surface. Furthermore, in relation to the controllability of surface impurity concentration, the deeper diffusion depth of opposite conductivity type regions impedes miniaturization due to current leakage caused by bunch-through between adjacent capacitors. There are also problems.

(Problems to be Solved by the Invention) As described above, the conventional method has the disadvantage that the process becomes W1'Ii because the in-phase diffusion technique is used to form the opposite conductivity type region on the side surface of the trench. Furthermore, there is a drawback that miniaturization is hindered due to limitations due to current leakage due to bunch through between adjacent capacitors.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to easily manufacture a trench capacitor, and to make it possible to make the region of the conductivity type opposite to that of the substrate formed on the side surface of the trench shallow. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce current leakage due to bunch-through between adjacent capacitors, thereby achieving further miniaturization.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of selectively forming a recess or a projection on the main surface of a semiconductor substrate, and a step of forming a recess or a projection on the main surface of a semiconductor substrate. The step of ion-implanting impurities obliquely into at least one side surface at a predetermined angle θ with respect to the perpendicular to the plane of the substrate.

(Function) In the method for manufacturing a semiconductor device of the present invention, impurities are applied to the side surfaces of recesses or protrusions selectively formed on the main surface of a semiconductor substrate at a predetermined angle θ with respect to the perpendicular to the plane of the substrate. By implanting ions from oblique directions, the depth of the ion implantation region formed on the side surface of the concave or convex portion can be increased by Sinθ (Sinθ × 1) compared to when θ is 0 degrees.
) is made to be twice as shallow.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing the manufacturing process according to the method of the present invention.

First, as in the conventional case, for example, a P-type silicon substrate 1
After a silicon oxide film 12 is deposited on the entire surface of the silicon oxide film 112 by CVD (chemical vapor deposition), this silicon oxide film 112 is patterned by photolithography or the like. Furthermore, using this patterned silicon oxide film 12 as a mask, the silicon substrate 11 is etched by RIE (reactive ion etching technique) to form a trench 13 with a depth of, for example, 4 μm (FIG. 1(a)). .

Then, using the silicon oxide 1112 as a mask, an N-type impurity such as phosphorus (P) is added to the trench 1 at an acceleration energy of 100 KeV and a dose of 1xiots/Cm2.
Ions are implanted from the frontage of trench 13 to form continuous N-type ion implantation regions 14 on the side and bottom surfaces of trench 13.

At this time, the angle θ with respect to the perpendicular to the plane of the substrate 11 is ±7
The ion implantation angle is set so that the ion implantation angle is approximately 1.5 degrees (Fig. 1 (b)).

Furthermore, when the shape of the frontage of the trench 13 is rectangular as shown in the plan view of FIG. Ion implantation is performed at a predetermined angle θ. In such a case, with respect to the two short sides, ions are implanted from the long sides at the same time into the side surfaces in the short sides.

Next, after removing the silicon oxide 1B 112, a thermal oxide film 15 is formed to a thickness of, for example, about 150 layers. The ion implantation region 14 is activated by this thermal oxidation step. Thereafter, a trench capacitor is completed by depositing polycrystalline silicon 1116, which is an electrode material, on the thermal oxide film 15 (FIG. 1(C)).

As described above, according to the method of the above embodiment, since the conventional solid-phase diffusion technology is not used, the diffusion impurity source layer (conventional As5Gl deposition process, thermal diffusion process and diffusion process from this diffusion impurity am) The step of removing the impurity source layer is not necessary, and these steps can be performed only by the ion implantation step.Therefore, the manufacturing process is simpler than the conventional method.

Furthermore, in the above embodiment, when forming the ion implantation region 14, the ion implantation angle is set so that the angle θ with respect to the perpendicular to the plane of the substrate 11 is approximately ±7 degrees, so that the side surface of the trench 13 is The depth of the ion implantation region 14 is sin θ (sin θ × 1
) can be formed twice as shallow. Here, the problem of current leakage due to punch-through or the like between adjacent capacitors is related to the depth of a region of a conductivity type opposite to that of the substrate formed on the side surface of the trench. That is, the shallower the depth of this region, the more suppressed is the occurrence of current flow due to bunch-through and the like. Therefore, in the trench capacitor formed by the method of the above embodiment, the distance between adjacent capacitors can be made smaller than that by the conventional method, thereby making it possible to miniaturize the device.

In the above embodiment, the ion implantation angle θ was set to about ±7 degrees, but as shown in the cross-sectional view of FIG. When the length of the frontage of the trench 13 is a and the trench depth is d, in order for ions to be implanted into all surfaces inside the trench in the next ion implantation process, the implantation angle θ must be set as follows. You need to set it to a value like an expression.

θ4arctan(j2/d) . . . 1 That is, if ion implantation is performed under the angle conditions given by the above equation 1, it is possible to form an ion implantation region that is continuous on the side and bottom surfaces inside the trench.

Further, when the trench depth d is relatively deep, the depth D of the ion implantation region formed on the side surface of the trench is given by the following equation.

D-ffi/lan θ...2 Therefore, the substantial depth D of the trench capacitor can be determined by the length of the frontage of the trench 13 °C and the ion implantation angle θ.

FIG. 4 is a sectional view showing the steps of a different embodiment of the present invention. In this embodiment, after the process shown in FIG. 1(b) is completed, impurity ions of the same conductivity type as the substrate 11, such as boron (B), are implanted in the same manner as when forming the N-type ion implantation region 14. A P-type ion implantation region 17 is formed by implanting ions inside the region 14 at an angle θ.

After this, the silicon oxide film 12 is removed in the same way as in the case of FIG. The trench capacitor is completed by depositing a polycrystalline silicon layer 16 of .

The trench capacitor formed by this method has a structure in which a P-type wA region is formed inside an N-type region, so the capacitance value as a capacitor can be increased, and the so-called HiC effect can be prevented. It becomes a structure that has. Furthermore, this structure is resistant to soft errors caused by alpha rays and the like.

FIG. 5(a) is a sectional view showing a process according to another embodiment of the present invention, and FIG. 5(b) is a plan view of the pattern. As mentioned above, in trench capacitors, the problem of current leakage due to punch-through between adjacent capacitors is related to the depth of the region of conductivity type opposite to that of the substrate formed on the sides of the trench; It is important to make the conductivity type region shallower.

Therefore, in the method of this embodiment, ion implantation is performed only on one side of the trench 13 formed in the substrate 11 under the same conditions as described above, and the ion implantation region 14 is formed only on one side of the trench 13. It was designed to do so.

A trench capacitor formed in this way is
A region of the conductivity type opposite to that of the substrate is formed only on one side surface of the trench, and no region of the opposite conductivity type is formed on the side surface opposite to this. Therefore, a sufficient punch-through withstand voltage can be ensured between the surface where the region of the opposite conductivity type is not formed and other trench capacitors, and further miniaturization is possible. Furthermore, from the viewpoint of the manufacturing process, since the ion implantation process only needs to be performed once, the process can be shortened.

Note that by making the planar shape of the frontage of the trench 13 not rectangular but polygonal, for example, hexagonal as shown in FIG. can. Making the planar shape of the frontage of the trench 13 polygonal in this manner is also effective in each of the embodiments shown in FIGS. 1 and 4.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in each of the above embodiments, a case has been described in which the present invention is applied to a method of manufacturing a semiconductor device having a trench capacitor. It goes without saying that the same method can be applied to a semiconductor a@ in which a capacitor is formed on the side surface of a convex portion by forming a region of the opposite conductivity type.

[Effects of the Invention] As described above, according to the present invention, ions are implanted obliquely into the side surfaces of the recesses or projections formed in the base to form a region of the opposite conductivity type to that of the base. Therefore, the process can be significantly simplified compared to conventional methods. Moreover, since ions are implanted obliquely at an implantation angle θ, the depth of the region of the conductivity type opposite to that of the substrate becomes sin θ times as much as when ions are implanted vertically as in the case of a planar capacitor. Therefore, for example, if θ is set to about 7 degrees, the depth will be about 1/10 of the conventional depth, making it possible to realize an extremely shallow region.

As a result, miniaturization can be achieved and the capacity of the cell can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a process according to an embodiment of the present invention, FIG. 2 is a diagram showing a planar shape of a trench formed during the process of the above embodiment, and FIG. A cross-sectional view showing the cross-sectional shape of a trench formed during the process,
FIG. 4 is a sectional view showing one step according to a method according to another embodiment of the present invention, FIG. 5 is a sectional view and pattern plan view showing one step according to a method according to another embodiment of the present invention, and FIG. The figure is a sectional view showing the steps of a conventional method. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Silicon oxide film, 13... Trench, 14... N-type ion implantation region, 15... Thermal oxide film, 16... Polycrystalline silicon layer , 17...P- type ion implantation region. Applicant's agent Patent attorney Takehiko Suzue (a) (b) (C) Figure 1 Figure 2 Figure 3 Figure 4 (a) (b) Figure 5 (a) b (b) (C) Figure 6 figure

Claims (1)

[Claims] 1. A step of selectively forming a concave portion or a convex portion on the main surface of a semiconductor substrate, and forming a predetermined angle θ with respect to a perpendicular to a plane of the substrate with respect to at least one side of the concave portion or convex portion. A method for manufacturing a semiconductor device, comprising the step of ion-implanting impurities from oblique directions. 2. Impurity ions are implanted obliquely at a predetermined angle θ with respect to the perpendicular to the plane of the base body into at least one side surface of the recess or the convex portion and the opposite side surface, respectively. A method for manufacturing a semiconductor device according to item 1. 3 When the depth of the recess or the height of the protrusion is d, and one side of the frontage of the recess or protrusion is l, the impurity implantation angle θ during the ion implantation satisfies θ≧arctan.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is set to have a relationship of (l/d). 4. The method of manufacturing a semiconductor device according to claim 1, wherein the conductivity type of the ions implanted in the ion implantation step is opposite to that of the substrate.