JPS63227036A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a leakage current between adjacent cell capacitors by forming channel stop layer on a recess bottom and also on the side by suitably selecting the angle of an ion beam, and locally increasing the impurity concentration of the lower corner of the recess. CONSTITUTION:After a recess 3 is formed on a silicon substrate 1, an N-type or P-type impurity is implanted to the side of the recess 3 to form, for example, a capacity electrode 5, the impurity is obliquely implanted to the bottom and sides of the recess 3 to form a channel stop. Then, after an insulating film 9 is formed on the surface of the recess 6, other capacity electrode is, for example, formed on the film 9 to form a capacitor. The impurity provides of an N<+> type layer 5 and a P<+> type layer 9 can be controlled by ion beam implanting angle, amount and energy to a wafer. Particularly, the impurity concentration can be locally enhanced by oblique ion implanting near the lower corner of the recess 6. Thus, it can prevent a leakage current between adjacent cell capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, particularly a dynamic RA
The present invention relates to a method of forming an isolation region between elements such as M.

2. Description of the Related Art In the manufacture of conventional dynamic RAMs, grooved capacitors have been proposed in order to increase the capacity of memory cells for storing signal charges as density increases.

This proposal, as shown in FIG.
After forming a recess 3 by etching (on Itching), arsenic ion beam 4 is obliquely implanted into the side and bottom surfaces of the recess 3 using resist or oxide film 2 as a mask to form an n+ layer 5 (second figure&).

Next, using the resist or oxide film 2 as a mask for selective etching, the bottom of the recess 3 is etched by RIE so that the n+ layer 6 at the bottom of the recess 3 is removed to form the recess 6, and then the resist or oxide film 2 is etched. Using as a mask, a boron ion beam 7 is implanted almost perpendicularly to the bottom surface of the recess 6 to form a p+ layer 8 (FIG. 2b).

Next, the resist or oxide film 2 is removed, an oxide film 9ff: is formed on the silicon substrate 1, and CVD (Chemical
After depositing polysilicon/10 by a vapor deposition method, the polysilicon 1o is planarized using a Nino F-7 vacuum, and the polysilicon 1o is removed leaving only the cell plate portion (FIG. 2C).

Problems to be Solved by the Invention In the conventional memory cell structure, a boron ion beam is implanted almost perpendicularly to the wafer in order to separate adjacent cell capacitance parts, and a channel stopper 9 is implanted only at the bottom of the groove.
A layer was formed to suppress leakage current flowing between cell capacitances. However, as the groove width becomes narrower, the width of the channel stop p region also becomes narrower, so that the leakage current 11 increases.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional element isolation method, it is an object of the present invention to provide a method for preventing leakage current between adjacent cell capacitance sections.

Means for Solving the Problems After forming a recess in a silicon substrate, n is formed on the side surface of the recess.
After implanting p-type or p-type impurities to form, for example, a capacitor electrode, p-type or n-type impurities are implanted into the bottom and side surfaces of the recess.
Type impurities are implanted obliquely to form channel stops. Next, after forming an insulating film on the surface of the recess, a capacitor is formed by forming, for example, the other capacitor electrode on the insulating film.

The impurity profiles of the working n+ and p+ layers can be controlled by the implantation angle of the ion beam relative to the wafer, the implantation dose, and the implantation energy. Particularly near the lower corner of the recess, the impurity concentration can be locally increased by oblique ion implantation.

Embodiment An embodiment of the present invention will be described with reference to FIG. 1st
The figure shows the manufacturing process of a grooved capacitor section of a memory cell section of a dynamic random access memory.

First, the silicon substrate 1 is etched by RIM using the resist or oxide film 2 as a mask for selective etching to form the recess 3, and then the side and bottom surfaces of the recess 3 are etched using the resist or oxide film 2 as a mask. An arsenic ion beam 4 is implanted obliquely to form an n+10 layer (FIG. 1a). This layer 5 becomes, for example, a capacitive electrode of a memory element.

Next, using the resist or oxide film 2 as a mask for selective etching, the bottom iRI of the recess 3 is removed so that the n layer 6 at the bottom of the four parts 3 is removed. ! : After forming the recess 6 by etching, a boron ion beam 7 is applied to the bottom and side surfaces of the recess 6 using the resist or oxide film 2 as a mask.
is implanted to form a p+ layer for channel stop (
Figure 1 b).

Next, the resist or oxide film 2 is removed, an oxide film 9 is formed on the silicon substrate 1, and a polysilicon layer 10 is formed by CVD.
After depositing polysilicon 10, the polysilicon 10 is planarized by etching back, and the polysilicon 10 is removed leaving only the cell plate portion (FIG. 1C). Polysilicon 1o becomes the other capacitor electrode.

Effects of the Invention According to the present invention, by appropriately selecting the angle of the ion beam, a channel stop layer can be formed not only on the bottom surface but also on the side surfaces of the recess, and the impurity concentration at the lower corner of the recess can be locally reduced. Since the height can be increased, the effective width of the channel stop region increases, and leakage current flowing between adjacent cell capacitance parts can be reduced.

In addition, by selecting appropriate ion beam angle, dose, and energy, it is possible to form a channel stop and at the same time create an HIC structure with a p-n junction in the capacitor, increasing the cell capacity and increasing the cell capacity. It also has the additional effect of preventing internal leakage current.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a grooved capacitor part according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of the conventional capacitor part. 1...Silicon substrate, 2...Resist or oxide film, 3...Concave portion, 4...Arsenic ion beam, 6...N+ Layer, 6...
Concave portion, 7...Boron ion beam, 8...
-p soil layer, 9...oxide film, 1o...polysilicon.

Claims (1)

[Claims] a step of forming a recess in a semiconductor substrate; a step of ion-implanting an n-type or p-type impurity into the side surface of the recess to form an n-layer or p-layer for an electrode on the side surface of the recess; Manufacturing a semiconductor device comprising the steps of forming a p-layer or n-layer for suppressing an inversion channel by obliquely ion-implanting p-type or n-type impurities into the side surface, and forming an insulating film on the surface of the recess. Method.