CN107403726A - The preparation method of semiconductor devices - Google Patents
The preparation method of semiconductor devices Download PDFInfo
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- CN107403726A CN107403726A CN201610341694.4A CN201610341694A CN107403726A CN 107403726 A CN107403726 A CN 107403726A CN 201610341694 A CN201610341694 A CN 201610341694A CN 107403726 A CN107403726 A CN 107403726A
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- nitride layer
- side wall
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- battery lead
- lead plate
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- 238000002360 preparation method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 150000004767 nitrides Chemical class 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000001312 dry etching Methods 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 6
- 239000011231 conductive filler Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 description 12
- 230000005611 electricity Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Present invention is disclosed a kind of preparation method of semiconductor devices, including：A capacitance structure is provided, the capacitance structure includes substrate, the nitride layer on the substrate and the patterned battery lead plate on the nitride layer；An offset side wall is prepared, the offset side wall at least covers the side wall of the battery lead plate；Dry etching is carried out to the nitride layer exposed, and removes the top of the nitride layer exposed；And the nitride layer to exposing carries out wet etching, and remove the bottom of the nitride layer exposed.The preparation method of semiconductor devices provided by the invention can effectively avoid the undercut problem of the nitride layer, and be advantageous to control production cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of preparation method of semiconductor devices.
Background technology
The development of electronic device, it experienced electron tube, transistor, integrated circuit, super large-scale integration
Four-stage.Integrated circuit experienced at a terrific speed small scale integration (Small Scale Integrate,
Referred to as SSI), large scale integrated circuit (Large Scale Integrate, referred to as LSI), super large rule
Vlsi die (Very Large Scale Integrate, referred to as VLSI), ULSI (Ultra
Large Scale Integrate, referred to as ULSI) etc. some developing stage.The manufacture work of integrated circuit simultaneously
Skill is also rapidly developing, at present, the manufacturing process of integrated circuit be broadly divided into diffusion, photoetching, etching,
6 film (thin film), ion implanting and polishing technical process, and the method by successively preparing, shape
Into final device architecture.
In existing integrated circuit preparation technology, nitride is passed through frequently as etching stop layer or dielectric insulation layer
Use, finally removing unnecessary nitride, carved especially in the case where nitride layer is thicker, it is necessary to cross
Erosion removes unnecessary nitride layer totally, however, when removing unnecessary nitride layer using wet etching,
Often form the incision (undercut) of nitride layer.As shown in figure 1, formed with nitridation in substrate 10
Nitride layer 11, formed with mask layer 12 on nitride layer 11, when being mask to nitride layer 11 with mask layer 12
When carrying out wet-etching technology, the side wall of nitride layer 11 can form incision 13, and incision 13 may cause leak
Electricity, have a strong impact on the performance of device.
In the prior art, to avoid incision 13 from impacting device, following two methods can be used：The
First, dry etching is carried out to nitride layer 11, still, dry etching needs etching gas to the He of substrate 10
Nitride layer 11 has higher selection ratio and is difficult control etching stopping position；Secondth, increase additionally
Photomask avoids electric leakage caused by incision 13, still, increase to increase the characteristic size of nitride layer 11
Extra photomask can increase process costs.
The content of the invention
It is an object of the present invention to provide a kind of preparation method of semiconductor devices, electric capacity can be effectively controlled
The problems such as being leaked electricity in structure caused by nitride layer incision.
In order to solve the above technical problems, the present invention provides a kind of preparation method of semiconductor devices, including：
One capacitance structure is provided, the capacitance structure include substrate, the nitride layer on the substrate,
And the patterned battery lead plate on the nitride layer；
An offset side wall is prepared, the offset side wall at least covers the side wall of the battery lead plate；
Dry etching is carried out to the nitride layer exposed, and removes the nitride layer exposed
Top；And
Wet etching is carried out to the nitride layer exposed, and removes the nitride layer exposed
Bottom.
Further, the preparation method of the semiconductor devices includes：
Using the battery lead plate as mask, dry etching is carried out to the nitride layer exposed, and remove sudden and violent
The top of the nitride layer exposed, form the side wall of the nitride layer；
The offset side wall is prepared, the offset side wall covers the side wall of the battery lead plate and the nitride
The side wall of layer.
Further, the preparation method of the semiconductor devices includes：
The offset side wall is prepared, the offset side wall covers the side wall of the battery lead plate；
Using the offset side wall and the battery lead plate as mask, dry method is carried out to the nitride layer exposed
Etching, and remove the top of the nitride layer exposed.
Further, during the nitride layer to exposing carries out dry etching, described in removal
The thickness on nitride layer top accounts for more than the 2/3 of the integral thickness of the nitride layer.
Further, the step of one capacitance structure of the offer includes：
The substrate is provided, includes mononitride layer on the substrate；
A plate electrode layer is formed on the nitride layer；
The graphical plate electrode layer, to form the battery lead plate.
Further, the step of one offset side wall of the preparation includes：
One pre- side wall layer of the preparation, the pre- side wall layer at least cover the top of the battery lead plate, the electricity
The top of the side wall of pole plate and the nitride layer exposed；
The pre- side wall at the top of the nitride layer for removing the top of the battery lead plate and exposing
Layer, forms the offset side wall.
Further, the capacitance structure also includes deep trench, the deep trench be located at the nitride layer and
In substrate, and positioned at the lower section of the battery lead plate, conductive filler is filled with the deep trench, it is described
Formed with a dielectric layer between the inwall of deep trench and the conductive filler.
Further, the material of the battery lead plate is polysilicon or metal.
Further, the perpendicular shape of the side wall of the battery lead plate.
Further, the material of the offset side wall is dielectric material.
Compared with prior art, the preparation method of semiconductor devices provided by the invention has advantages below：
In the preparation method of semiconductor devices provided by the invention, the offset side wall at least covers the electricity
The side wall of pole plate, then, dry etching first is carried out to the nitride layer exposed, and remove and expose
The nitride layer top, and then the nitride layer to exposing carry out wet etching, and
The bottom of the nitride layer exposed is removed, because the wet etching is only with the removal nitride layer
Bottom, so during the wet etching, the side wall of the nitride layer is retained, will not
Form incision；In addition, the preparation method of semiconductor devices provided by the invention can conveniently be incorporated into it is existing
In technological process, it is beneficial to control manufacturing cost.
Brief description of the drawings
There is the structural representation of incision for nitride layer in the prior art in Fig. 1；
Fig. 2 is the flow chart of the preparation method of first embodiment semiconductor devices in the present invention；
Fig. 3-Fig. 8 is structural representation of the semiconductor devices of first embodiment of the invention in preparation process；
Fig. 9 is the flow chart of the preparation method of second embodiment semiconductor devices in the present invention；
Figure 10-Figure 13 is structural representation of the semiconductor devices of second embodiment of the invention in preparation process.
Embodiment
The preparation method of the semiconductor devices of the present invention is described in more detail below in conjunction with schematic diagram,
Which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change and be described herein
The present invention, and still realize the present invention advantageous effects.Therefore, description below be appreciated that for
Those skilled in the art's is widely known, and is not intended as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, public affairs are not described in detail
The function and structure known, because they can make the present invention chaotic due to unnecessary details.It will be understood that
In the exploitation of any practical embodiments, it is necessary to a large amount of implementation details are made to realize the specific objective of developer,
Such as according to the limitation about system or about business, another embodiment is changed into by one embodiment.Separately
Outside, it will be understood that this development is probably complicated and time-consuming, but for people in the art
It is only routine work for member.
More specifically description is of the invention by way of example referring to the drawings in the following passage.According to it is following explanation and
Claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simple
The form of change and use non-accurately ratio, only to it is convenient, lucidly aid in illustrating the embodiment of the present invention
Purpose.
The core concept of the present invention is, there is provided a kind of preparation method of semiconductor devices, including：
One capacitance structure is provided, the capacitance structure include substrate, the nitride layer on the substrate,
And the patterned battery lead plate on the nitride layer；
An offset side wall is prepared, the offset side wall at least covers the side wall of the battery lead plate；
Dry etching is carried out to the nitride layer exposed, and removes the nitride layer exposed
Top；And
Wet etching is carried out to the nitride layer exposed, and removes the nitride layer exposed
Bottom.
By above-mentioned steps, it is possible to prevente effectively from forming incision in the nitride layer, and incision is effectively avoided
Caused by the problems such as leaking electricity, and be beneficial to control manufacturing cost.
Several embodiments of the preparation method of the semiconductor devices are exemplified below, with the clear explanation present invention's
Content, it is understood that, present disclosure is not restricted to following examples, and other pass through this area
The improvement of the conventional technical means of those of ordinary skill is also within the thought range of the present invention.
First embodiment
The preparation method that Fig. 2-Fig. 8 illustrates the semiconductor devices of the present invention is referred to below, wherein, Fig. 2
For the flow chart of the preparation method of first embodiment semiconductor devices in the present invention；Fig. 3-Fig. 8 is the present invention the
Structural representation of the semiconductor devices of one embodiment in preparation process.In the present embodiment, first to exposure
The nitride layer gone out carries out dry etching, then prepares the offset side wall, and the offset side wall covers institute
The side wall of battery lead plate and the side wall of the nitride layer are stated, is comprised the following steps that described.
First, step S11 is carried out, there is provided a capacitance structure, specifically, as shown in Figure 3, there is provided a substrate
100, include mononitride layer 110 on the substrate 100, the nitride layer 110 can pass through low pressure
The technique such as vapour deposition process or plasma enhanced chemical vapor deposition method is learned to prepare；In the nitride layer 110
One plate electrode layer 120 of upper formation；As shown in figure 4, the graphical plate electrode layer 120, to form the electricity
Pole plate 121.Wherein, the process of the graphical plate electrode layer 120 can use photoetching and dry etch process,
This is it will be understood by those skilled in the art that therefore not to repeat here.
As shown in figure 4, the capacitance structure 190 formed includes substrate 100, positioned at the substrate 100
On nitride layer 110 and the patterned battery lead plate 121 on the nitride layer 110, it is described
Capacitance structure 190 also includes deep trench 101, and the deep trench 101 is located at the nitride layer 110 and substrate
In 100, and conductive filler is filled with the lower section of the battery lead plate 121, the deep trench 101
102, formed with a dielectric layer 103 between the inwall and the conductive filler 102 of the deep trench 101.
Preferably, the material of the battery lead plate 121 is polysilicon or metal, and metal includes titanium, tantalum, tungsten, nitridation
One or more of alloys in titanium, tantalum nitride and tungsten nitride.In the present embodiment, by graphical institute
The process for stating plate electrode layer 120 uses photoetching and dry etch process, so, the side of the battery lead plate 121
The perpendicular shape of wall.
Then, step S12 is carried out, as shown in figure 5, being mask with the battery lead plate 121, to what is exposed
The nitride layer 110 carries out dry etching, and removes the top of the nitride layer 110 exposed,
Form the side wall 110a of the nitride layer 110.Preferably, remove the thickness on the top of nitride layer 110
Degree L2 accounts for more than the 2/3 of the integral thickness L1 of the nitride layer 110, to remove the nitrogen exposed
The major part of compound layer 110.Dry etching is used in this step, dry etching is anisotropic etching,
The side wall 110a patterns of the nitride layer 110 formed are good, will not form incision.
Afterwards, step S13 is carried out, prepares offset side wall, the offset side wall covers the battery lead plate 121
Side wall and the nitride layer 110 side wall；Specifically, the step S13 includes：Such as Fig. 6 institutes
Show, it is described preparation one pre- side wall layer 130, the pre- side wall layer 130 cover the battery lead plate 121 top,
The side wall of the battery lead plate 121, the side wall 110a of the nitride layer 110 and the nitridation exposed
The top of nitride layer 110；As shown in fig. 7, the pre- side wall layer 130 at the top of the battery lead plate 121 is removed,
The pre- side wall layer 130 at the top of nitride layer 110 is removed simultaneously, forms the offset side wall 131.
Preferably, the material of the offset side wall 131 is dielectric material, such as oxide or nitride.
Then, step S14 is carried out, as shown in figure 8, carrying out wet method to the nitride layer 110 exposed
Etching, and remove the bottom of the nitride layer 110 exposed.In this step, due to the wet method
Etching only only needs to remove the institute of sub-fraction with the bottom for removing the nitride layer 110, the wet etching
Nitride layer 110 is stated, so, during the wet etching, although the wet etching is isotropism
Etching, the side wall of the nitride layer 110 of bottom are retained, and will not form incision；Also,
During the wet etching, the offset side wall 131 can prevent the nitride layer 110 on top
Side wall is etched；In addition, the offset side wall 131 can be used as side wall to protect, without subsequently being removed.
Second embodiment
Fig. 9-13 are referred to, wherein, Fig. 9 is the preparation method of second embodiment semiconductor devices in the present invention
Flow chart；Figure 10-Figure 13 is structure of the semiconductor devices of second embodiment of the invention in preparation process
Schematic diagram, in Figure 10-Figure 13, reference number represents and the statement of Fig. 3-Fig. 8 identicals and the first embodiment party
Formula identical part.The preparation method of the preparation method of the second embodiment and the first embodiment is basic
Identical, its difference is：The offset side wall is first prepared, the offset side wall covers the side of the battery lead plate
Wall；Again using the offset side wall and the battery lead plate as mask, the nitride layer exposed is done
Method etches, and comprises the following steps that described.
Step S21 in the present embodiment is identical with the step S11 of first embodiment, and therefore not to repeat here.
Step S22 is carried out, prepares the offset side wall, specifically, as shown in Figure 10, the preparation one is pre-
Side wall layer 230, the pre- side wall layer 230 cover the top of the battery lead plate 121, the battery lead plate 121
The top of side wall and the nitride layer 110 exposed；As shown in figure 11, the battery lead plate 121 is removed
Top the pre- side wall layer 230, while remove the pre- side wall layer at the top of the nitride layer 110
230, the offset side wall 231 is formed, the offset side wall 231 covers the side wall of the battery lead plate 121；
Step S23 is carried out afterwards, as shown in figure 12, with the offset side wall 231 and the battery lead plate 121
For mask, dry etching is carried out to the nitride layer 110 exposed, and remove the nitrogen exposed
The top of compound layer 110.Preferably, the thickness L4 for removing the top of nitride layer 110 accounts for the nitridation
More than the 2/3 of the integral thickness L3 of nitride layer 110, to remove the big portion of the nitride layer 110 exposed
Point.Use dry etching in this step, dry etching is anisotropic etching, the nitridation formed
The sidewall profile of nitride layer 110 is good, will not form incision.
Then, step S24 is carried out, as shown in figure 13, the nitride layer 110 exposed is carried out wet
Method etches, and removes the bottom of the nitride layer 110 exposed.In this step, due to described wet
Method etching only only needs to remove sub-fraction with the bottom for removing the nitride layer 110, the wet etching
The nitride layer 110, so, during the wet etching, although the wet etching is each to same
Property etching, the side wall of the nitride layer 110 of bottom is retained, and will not form incision；Also,
When carrying out dry etching described in step S23, the setting of the offset side wall 231 can increase capped
The characteristic size of the nitride layer 110, so as to increase the characteristic size of the final nitride layer 110,
It is possible to prevente effectively from the problems such as being leaked electricity caused by incision；In addition, the offset side wall 231 can be used as side wall
Protection, without subsequently being removed.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the present invention
Bright spirit and scope.So, if the present invention these modifications and variations belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
- A kind of 1. preparation method of semiconductor devices, it is characterised in that including：One capacitance structure is provided, the capacitance structure include substrate, the nitride layer on the substrate, with And the patterned battery lead plate on the nitride layer；An offset side wall is prepared, the offset side wall at least covers the side wall of the battery lead plate；Dry etching is carried out to the nitride layer exposed, and removes the upper of the nitride layer exposed Portion；AndWet etching is carried out to the nitride layer exposed, and removes the bottom of the nitride layer exposed Portion.
- 2. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the semiconductor The preparation method of device includes：Using the battery lead plate as mask, dry etching is carried out to the nitride layer exposed, and remove exposure The top of the nitride layer gone out, form the side wall of the nitride layer；The offset side wall is prepared, the offset side wall covers the side wall of the battery lead plate and the nitride layer Side wall.
- 3. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the semiconductor The preparation method of device includes：The offset side wall is prepared, the offset side wall covers the side wall of the battery lead plate；Using the offset side wall and the battery lead plate as mask, is carried out to the nitride layer exposed dry method quarter Erosion, and remove the top of the nitride layer exposed.
- 4. the preparation method of the semiconductor devices as described in any one in claims 1 to 3, its feature exists In, to exposing the nitride layer carry out dry etching during, remove on the nitride layer The thickness in portion accounts for more than the 2/3 of the integral thickness of the nitride layer.
- 5. the preparation method of the semiconductor devices as described in any one in claims 1 to 3, its feature exists In described the step of providing a capacitance structure includes：The substrate is provided, includes mononitride layer on the substrate；A plate electrode layer is formed on the nitride layer；The graphical plate electrode layer, to form the battery lead plate.
- 6. the preparation method of the semiconductor devices as described in any one in claims 1 to 3, its feature exists In described the step of preparing an offset side wall includes：One pre- side wall layer of the preparation, the pre- side wall layer at least cover the top of the battery lead plate, the electrode The top of the side wall of plate and the nitride layer exposed；The pre- side wall layer at the top of the nitride layer for removing the top of the battery lead plate and exposing, Form the offset side wall.
- 7. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the capacitive junctions Structure also includes deep trench, and the deep trench is located in the nitride layer and substrate, and is located at the battery lead plate Lower section, be filled with conductive filler in the deep trench, the inwall of the deep trench is filled out with the conduction Fill between thing formed with a dielectric layer.
- 8. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the battery lead plate Material be polysilicon or metal.
- 9. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the battery lead plate The perpendicular shape of side wall.
- 10. the preparation method of semiconductor devices as claimed in claim 1, it is characterised in that the skew side The material of wall is dielectric material.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63227036A (en) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| TW406405B (en) * | 1998-11-26 | 2000-09-21 | Nanya Plastics Corp | Manufacture method of the trench-type capacitor |
| CN1354889A (en) * | 1999-06-09 | 2002-06-19 | 因芬尼昂技术北美公司 | Method for expanding trenches by anisotropic wet etch |
| CN1364312A (en) * | 1999-07-26 | 2002-08-14 | 因芬尼昂技术北美公司 | Method of making buried strap for trench capacitor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Bilateral Corner Rounding Process for Partially Vertical Memory Cells |
| US20050282393A1 (en) * | 2004-06-16 | 2005-12-22 | International Business Machines Corporation | Structure and method for collar self-aligned to buried plate |
| CN101064282A (en) * | 2006-04-24 | 2007-10-31 | 联华电子股份有限公司 | Trench capacitor dynamic random access memory element and manufacturing method thereof |
-
2016
- 2016-05-20 CN CN201610341694.4A patent/CN107403726B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63227036A (en) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| TW406405B (en) * | 1998-11-26 | 2000-09-21 | Nanya Plastics Corp | Manufacture method of the trench-type capacitor |
| CN1354889A (en) * | 1999-06-09 | 2002-06-19 | 因芬尼昂技术北美公司 | Method for expanding trenches by anisotropic wet etch |
| CN1364312A (en) * | 1999-07-26 | 2002-08-14 | 因芬尼昂技术北美公司 | Method of making buried strap for trench capacitor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Bilateral Corner Rounding Process for Partially Vertical Memory Cells |
| US20050282393A1 (en) * | 2004-06-16 | 2005-12-22 | International Business Machines Corporation | Structure and method for collar self-aligned to buried plate |
| CN101064282A (en) * | 2006-04-24 | 2007-10-31 | 联华电子股份有限公司 | Trench capacitor dynamic random access memory element and manufacturing method thereof |
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