CN107403726B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN107403726B CN107403726B CN201610341694.4A CN201610341694A CN107403726B CN 107403726 B CN107403726 B CN 107403726B CN 201610341694 A CN201610341694 A CN 201610341694A CN 107403726 B CN107403726 B CN 107403726B
- Authority
- CN
- China
- Prior art keywords
- nitride layer
- side wall
- electrode plate
- semiconductor device
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
The invention discloses a preparation method of a semiconductor device, which comprises the following steps: providing a capacitor structure, wherein the capacitor structure comprises a substrate, a nitride layer positioned on the substrate, and a patterned electrode plate positioned on the nitride layer; preparing an offset side wall, wherein the offset side wall at least covers the side wall of the electrode plate; performing dry etching on the exposed nitride layer, and removing the upper part of the exposed nitride layer; and performing wet etching on the exposed nitride layer, and removing the bottom of the exposed nitride layer. The preparation method of the semiconductor device provided by the invention can effectively avoid the undercut problem of the nitride layer and is beneficial to controlling the production cost.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor device.
Background
The development of electronic devices goes through four stages, namely electron tubes, transistors, integrated circuits and ultra-large scale integrated circuits. Integrated circuits have undergone several stages of development at an extremely rapid rate, such as Small Scale Integration (SSI), Large Scale Integration (LSI), Very Large Scale Integration (VLSI), and Ultra Large Scale Integration (ULSI). Meanwhile, the manufacturing process of the integrated circuit is also rapidly developed, and at present, the manufacturing process of the integrated circuit is mainly divided into 6 processes of diffusion, photoetching, etching, thin film (film), ion implantation and polishing, and a final device structure is formed by a layer-by-layer preparation method.
In the existing integrated circuit manufacturing process, nitride is often used as an etching stop layer or a dielectric insulating layer, and finally, when the excess nitride is removed, especially when the nitride layer is relatively thick, over-etching is required to remove the excess nitride layer cleanly, however, when the excess nitride layer is removed by wet etching, undercutting (undercut) of the nitride layer is often formed. As shown in fig. 1, a nitride layer 11 is formed on a substrate 10, a mask layer 12 is formed on the nitride layer 11, and when the mask layer 12 is used as a mask to perform a wet etching process on the nitride layer 11, undercuts 13 are formed on the sidewalls of the nitride layer 11, and the undercuts 13 may cause current leakage, which seriously affects the performance of the device.
In the prior art, to avoid the influence of the undercut 13 on the device, the following two methods are adopted: first, the nitride layer 11 is dry etched, but the dry etching requires a high selection ratio of etching gas to the substrate 10 and the nitride layer 11 and it is difficult to control an etching stop position; second, adding an extra photo mask to increase the feature size of the nitride layer 11 avoids the leakage caused by the undercut 13, but the extra photo mask increases the process cost.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which can effectively control the problems of electric leakage and the like caused by undercutting of a nitride layer in a capacitor structure.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a capacitor structure, wherein the capacitor structure comprises a substrate, a nitride layer positioned on the substrate, and a patterned electrode plate positioned on the nitride layer;
preparing an offset side wall, wherein the offset side wall at least covers the side wall of the electrode plate;
performing dry etching on the exposed nitride layer, and removing the upper part of the exposed nitride layer; and
and carrying out wet etching on the exposed nitride layer, and removing the bottom of the exposed nitride layer.
Further, the preparation method of the semiconductor device comprises the following steps:
performing dry etching on the exposed nitride layer by taking the electrode plate as a mask, and removing the upper part of the exposed nitride layer to form the side wall of the nitride layer;
and preparing the offset side wall, wherein the offset side wall covers the side wall of the electrode plate and the side wall of the nitride layer.
Further, the preparation method of the semiconductor device comprises the following steps:
preparing the offset side wall, wherein the offset side wall covers the side wall of the electrode plate;
and carrying out dry etching on the exposed nitride layer by taking the offset side wall and the electrode plate as masks, and removing the upper part of the exposed nitride layer.
Further, during the dry etching process of the exposed nitride layer, the thickness of the upper part of the nitride layer is removed to be more than 2/3 of the whole thickness of the nitride layer.
Further, the step of providing a capacitor structure includes:
providing the substrate, wherein the substrate comprises a nitride layer;
forming an electrode plate layer on the nitride layer;
patterning the electrode plate layer to form the electrode plate.
Further, the step of preparing an offset sidewall spacer includes:
preparing a pre-side wall layer, wherein the pre-side wall layer at least covers the top of the electrode plate, the side wall of the electrode plate and the exposed top of the nitride layer;
and removing the top of the electrode plate and the exposed pre-side wall layer on the top of the nitride layer to form the offset side wall.
Furthermore, the capacitor structure further comprises a deep trench, the deep trench is located in the nitride layer and the substrate and below the electrode plate, conductive fillers are filled in the deep trench, and a dielectric layer is formed between the inner wall of the deep trench and the conductive fillers.
Further, the electrode plate is made of polysilicon or metal.
Furthermore, the side wall of the electrode plate is vertical.
Further, the offset side wall is made of a dielectric material.
Compared with the prior art, the preparation method of the semiconductor device provided by the invention has the following advantages:
in the preparation method of the semiconductor device, the offset side wall at least covers the side wall of the electrode plate, then the exposed nitride layer is subjected to dry etching firstly, the upper part of the exposed nitride layer is removed, then the exposed nitride layer is subjected to wet etching, and the bottom part of the exposed nitride layer is removed, and because the wet etching only removes the bottom part of the nitride layer, the side wall of the nitride layer is reserved in the wet etching process, and undercutting cannot be formed; in addition, the preparation method of the semiconductor device provided by the invention can be conveniently integrated into the existing process flow, and is beneficial to controlling the manufacturing cost.
Drawings
FIG. 1 is a schematic diagram of a prior art undercut of a nitride layer;
fig. 2 is a flowchart of a manufacturing method of a semiconductor device according to a first embodiment of the present invention;
fig. 3 to 8 are schematic structural views of a semiconductor device in a manufacturing process according to a first embodiment of the present invention;
fig. 9 is a flowchart of a method of manufacturing a semiconductor device according to a second embodiment of the present invention;
fig. 10 to 13 are schematic structural views of a semiconductor device according to a second embodiment of the present invention during the manufacturing process.
Detailed Description
The method of manufacturing a semiconductor device of the present invention will now be described in more detail with reference to the schematic drawings, in which preferred embodiments of the invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is to provide a preparation method of a semiconductor device, which comprises the following steps:
providing a capacitor structure, wherein the capacitor structure comprises a substrate, a nitride layer positioned on the substrate, and a patterned electrode plate positioned on the nitride layer;
preparing an offset side wall, wherein the offset side wall at least covers the side wall of the electrode plate;
performing dry etching on the exposed nitride layer, and removing the upper part of the exposed nitride layer; and
and carrying out wet etching on the exposed nitride layer, and removing the bottom of the exposed nitride layer.
Through the steps, undercutting in the nitride layer can be effectively avoided, the problems of electric leakage and the like caused by undercutting can be effectively avoided, and the manufacturing cost is favorably controlled.
The following examples of the method for manufacturing the semiconductor device are given to clearly illustrate the contents of the present invention, and it should be understood that the contents of the present invention are not limited to the following examples, and other modifications by conventional technical means of those skilled in the art are also within the scope of the idea of the present invention.
First embodiment
Referring to fig. 2 to 8, a method for fabricating a semiconductor device according to the present invention is described in detail, wherein fig. 2 is a flowchart illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention; fig. 3 to 8 are schematic structural views of a semiconductor device according to a first embodiment of the present invention during a manufacturing process. In this embodiment, the exposed nitride layer is dry-etched first, and then the offset sidewall is prepared, where the offset sidewall covers the sidewalls of the electrode plate and the nitride layer, and the specific steps are as follows.
Firstly, step S11 is performed to provide a capacitor structure, specifically, as shown in fig. 3, a substrate 100 is provided, the substrate 100 includes a nitride layer 110 thereon, and the nitride layer 110 may be prepared by a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method; forming an electrode plate layer 120 on the nitride layer 110; as shown in fig. 4, the electrode plate layer 120 is patterned to form the electrode plate 121. The process of patterning the electrode plate layer 120 may adopt a photolithography and a dry etching process, which can be understood by those skilled in the art and is not described herein again.
As shown in fig. 4, the formed capacitor structure 190 includes a substrate 100, a nitride layer 110 on the substrate 100, and a patterned electrode plate 121 on the nitride layer 110, the capacitor structure 190 further includes a deep trench 101, the deep trench 101 is located in the nitride layer 110 and the substrate 100 and below the electrode plate 121, the deep trench 101 is filled with a conductive filler 102, and a dielectric layer 103 is formed between an inner wall of the deep trench 101 and the conductive filler 102. Preferably, the electrode plate 121 is made of polysilicon or metal, and the metal includes one or more of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and tungsten nitride. In this embodiment, since the process of patterning the electrode plate layer 120 adopts photolithography and dry etching processes, the sidewall of the electrode plate 121 is vertical.
Next, step S12 is performed, as shown in fig. 5, the electrode plate 121 is used as a mask to perform dry etching on the exposed nitride layer 110, and the upper portion of the exposed nitride layer 110 is removed, so as to form a sidewall 110a of the nitride layer 110. Preferably, the thickness L2 of the upper portion of the nitride layer 110 is removed to be greater than 2/3 of the overall thickness L1 of the nitride layer 110, so as to remove most of the exposed nitride layer 110. In the step, dry etching is adopted, the dry etching is anisotropic etching, and the formed side wall 110a of the nitride layer 110 has good appearance and can not form undercutting.
Then, step S13 is performed to prepare an offset spacer, where the offset spacer covers the side wall of the electrode plate 121 and the side wall of the nitride layer 110; specifically, the step S13 includes: as shown in fig. 6, preparing a pre-side wall layer 130, wherein the pre-side wall layer 130 covers the top of the electrode plate 121, the sidewall 110a of the nitride layer 110, and the exposed top of the nitride layer 110; as shown in fig. 7, the pre-side wall layer 130 on the top of the electrode plate 121 is removed, and the pre-side wall layer 130 on the top of the nitride layer 110 is removed at the same time, so as to form the offset side wall 131. Preferably, the offset spacers 131 are made of a dielectric material, such as oxide or nitride.
Subsequently, step S14 is performed, as shown in fig. 8, a wet etching is performed on the exposed nitride layer 110, and the bottom of the exposed nitride layer 110 is removed. In this step, since the wet etching only removes the bottom of the nitride layer 110, the wet etching only needs to remove a small portion of the nitride layer 110, so that, in the wet etching process, although the wet etching is isotropic etching, the sidewall of the nitride layer 110 at the bottom is retained, and undercutting is not formed; in the wet etching process, the offset spacers 131 may prevent the sidewalls of the upper nitride layer 110 from being etched; in addition, the offset sidewall 131 may serve as a sidewall protection without subsequent removal.
Second embodiment
Referring to fig. 9-13, fig. 9 is a flow chart illustrating a method of fabricating a semiconductor device according to a second embodiment of the present invention; fig. 10 to 13 are schematic structural views of a semiconductor device according to a second embodiment of the present invention during the manufacturing process, and in fig. 10 to 13, the same reference numerals as those in fig. 3 to 8 denote the same components as those in the first embodiment. The method of manufacture of the second embodiment is substantially the same as the method of manufacture of the first embodiment, except that: firstly, preparing the offset side wall, wherein the offset side wall covers the side wall of the electrode plate; and performing dry etching on the exposed nitride layer by using the offset side wall and the electrode plate as masks, wherein the specific steps are as follows.
Step S21 in this embodiment is the same as step S11 in the first embodiment, and is not repeated here.
Performing step S22 to prepare the offset spacer, specifically, as shown in fig. 10, preparing a pre-side wall layer 230, where the pre-side wall layer 230 covers the top of the electrode plate 121, the side wall of the electrode plate 121, and the top of the exposed nitride layer 110; as shown in fig. 11, removing the pre-side wall layer 230 on the top of the electrode plate 121, and simultaneously removing the pre-side wall layer 230 on the top of the nitride layer 110 to form the offset side wall 231, where the offset side wall 231 covers the side wall of the electrode plate 121;
then, step S23 is performed, as shown in fig. 12, the exposed nitride layer 110 is dry etched by using the offset spacers 231 and the electrode plate 121 as masks, and the upper portion of the exposed nitride layer 110 is removed. Preferably, the thickness L4 of the upper portion of the nitride layer 110 is removed to be greater than 2/3 of the overall thickness L3 of the nitride layer 110, so as to remove most of the exposed nitride layer 110. In the step, dry etching is adopted, the dry etching is anisotropic etching, and the formed side wall of the nitride layer 110 has good appearance and can not form undercutting.
Subsequently, step S24 is performed, as shown in fig. 13, a wet etching is performed on the exposed nitride layer 110, and the bottom of the exposed nitride layer 110 is removed. In this step, since the wet etching only removes the bottom of the nitride layer 110, the wet etching only needs to remove a small portion of the nitride layer 110, so that, in the wet etching process, although the wet etching is isotropic etching, the sidewall of the nitride layer 110 at the bottom is retained, and undercutting is not formed; moreover, when the dry etching is performed in step S23, the arrangement of the offset spacers 231 may increase the feature size of the covered nitride layer 110, so as to increase the final feature size of the nitride layer 110, thereby effectively avoiding the problems of electrical leakage and the like caused by undercut; in addition, the offset sidewall 231 may serve as a sidewall protection without subsequent removal.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
providing a capacitor structure, wherein the capacitor structure comprises a substrate, a nitride layer positioned on the substrate, and a patterned electrode plate positioned on the nitride layer, the capacitor structure further comprises a deep trench, the deep trench is positioned in the nitride layer and the substrate and is positioned below the electrode plate, conductive fillers are filled in the deep trench, and a dielectric layer is formed between the inner wall of the deep trench and the conductive fillers;
preparing an offset side wall, wherein the offset side wall at least covers the side wall of the electrode plate;
performing dry etching on the exposed nitride layer, and removing the upper part of the exposed nitride layer, wherein the thickness of the upper part of the removed nitride layer is more than 2/3 of the whole thickness of the nitride layer in the process of performing dry etching on the exposed nitride layer; and
and carrying out wet etching on the exposed nitride layer, and removing the bottom of the exposed nitride layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device comprises:
performing dry etching on the exposed nitride layer by taking the electrode plate as a mask, and removing the upper part of the exposed nitride layer to form the side wall of the nitride layer;
and preparing the offset side wall, wherein the offset side wall covers the side wall of the electrode plate and the side wall of the nitride layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a semiconductor device comprises:
preparing the offset side wall, wherein the offset side wall covers the side wall of the electrode plate;
and carrying out dry etching on the exposed nitride layer by taking the offset side wall and the electrode plate as masks, and removing the upper part of the exposed nitride layer.
4. A method of manufacturing a semiconductor device according to any of claims 1 to 3, wherein the step of providing a capacitor structure comprises:
providing the substrate, wherein the substrate comprises a nitride layer;
forming an electrode plate layer on the nitride layer;
patterning the electrode plate layer to form the electrode plate.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step of manufacturing an offset spacer comprises:
preparing a pre-side wall layer, wherein the pre-side wall layer at least covers the top of the electrode plate, the side wall of the electrode plate and the exposed top of the nitride layer;
and removing the top of the electrode plate and the exposed pre-side wall layer on the top of the nitride layer to form the offset side wall.
6. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the electrode plate is polysilicon or metal.
7. The method for manufacturing a semiconductor device according to claim 1, wherein a side wall of the electrode plate is vertical.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the offset spacer is made of a dielectric material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610341694.4A CN107403726B (en) | 2016-05-20 | 2016-05-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610341694.4A CN107403726B (en) | 2016-05-20 | 2016-05-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107403726A CN107403726A (en) | 2017-11-28 |
| CN107403726B true CN107403726B (en) | 2019-12-27 |
Family
ID=60389375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610341694.4A Active CN107403726B (en) | 2016-05-20 | 2016-05-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107403726B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63227036A (en) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| TW406405B (en) * | 1998-11-26 | 2000-09-21 | Nanya Plastics Corp | Manufacture method of the trench-type capacitor |
| CN1354889A (en) * | 1999-06-09 | 2002-06-19 | 因芬尼昂技术北美公司 | Method for expanding trenches by anisotropic wet etch |
| CN1364312A (en) * | 1999-07-26 | 2002-08-14 | 因芬尼昂技术北美公司 | Method of making buried strap for trench capacitor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Process for making double corners round of partial vertical storage unit |
| CN101064282A (en) * | 2006-04-24 | 2007-10-31 | 联华电子股份有限公司 | Groove capacitance dynamic random access memory and its method for making the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7223669B2 (en) * | 2004-06-16 | 2007-05-29 | International Business Machines Corporation | Structure and method for collar self-aligned to buried plate |
-
2016
- 2016-05-20 CN CN201610341694.4A patent/CN107403726B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63227036A (en) * | 1987-03-17 | 1988-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| TW406405B (en) * | 1998-11-26 | 2000-09-21 | Nanya Plastics Corp | Manufacture method of the trench-type capacitor |
| CN1354889A (en) * | 1999-06-09 | 2002-06-19 | 因芬尼昂技术北美公司 | Method for expanding trenches by anisotropic wet etch |
| CN1364312A (en) * | 1999-07-26 | 2002-08-14 | 因芬尼昂技术北美公司 | Method of making buried strap for trench capacitor |
| CN1591834A (en) * | 2003-09-03 | 2005-03-09 | 南亚科技股份有限公司 | Process for making double corners round of partial vertical storage unit |
| CN101064282A (en) * | 2006-04-24 | 2007-10-31 | 联华电子股份有限公司 | Groove capacitance dynamic random access memory and its method for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107403726A (en) | 2017-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9653571B2 (en) | Freestanding spacer having sub-lithographic lateral dimension and method of forming same | |
| CN109786236B (en) | Etching and structures formed thereby | |
| US9117822B1 (en) | Methods and structures for back end of line integration | |
| US10269581B2 (en) | Method of fabricating a semiconductor structure | |
| CN108470710B (en) | A method of forming semiconductor storage | |
| US20190096760A1 (en) | Methods for Reducing Contact Depth Variation in Semiconductor Fabrication | |
| KR20190038945A (en) | Semi-atomic layer etching method of silicon nitride | |
| JP2011009636A (en) | Method for forming via hole | |
| KR100696884B1 (en) | Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure | |
| TWI593105B (en) | Method for forming semiconductor device structure | |
| US20170294535A1 (en) | Semiconductor device and fabrication method thereof | |
| CN108666263B (en) | Method for manufacturing contact hole | |
| EP3279932B1 (en) | A semiconductor device and manufacture thereof | |
| CN107403726B (en) | Method for manufacturing semiconductor device | |
| US9224803B2 (en) | Formation of a high aspect ratio contact hole | |
| JPH08288256A (en) | Trench etching method | |
| CN104701242B (en) | The lithographic method of contact hole | |
| CN107706147B (en) | Preparation method of vertical contact hole | |
| CN109755175B (en) | Interconnect structure and method of forming the same | |
| CN110349908B (en) | Self-aligned contact structure and method for forming the same | |
| CN108962742B (en) | Method for manufacturing semiconductor structure | |
| KR100842508B1 (en) | Method for manufacturing device isolation layer of semiconductor device | |
| CN112530857A (en) | Semiconductor structure and forming method thereof | |
| CN112531027B (en) | Semiconductor structure and forming method thereof | |
| CN112908841B (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |