JPS6373941U - - Google Patents

Info

Publication number
JPS6373941U
JPS6373941U JP16772386U JP16772386U JPS6373941U JP S6373941 U JPS6373941 U JP S6373941U JP 16772386 U JP16772386 U JP 16772386U JP 16772386 U JP16772386 U JP 16772386U JP S6373941 U JPS6373941 U JP S6373941U
Authority
JP
Japan
Prior art keywords
flat
package
semiconductor device
mount base
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16772386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16772386U priority Critical patent/JPS6373941U/ja
Publication of JPS6373941U publication Critical patent/JPS6373941U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のキヤツプを除いた
斜視図、第2図は従来のパツケージに半導体素子
を固定した状態のキヤツプなしの斜視図である。 1……ヘツダ、2,12……カソードリード、
3……アノードリード、4……マウントベース、
5……ダイオードペレツト、6……金属細線。
FIG. 1 is a perspective view of an embodiment of the present invention with the cap removed, and FIG. 2 is a perspective view of a conventional package with a semiconductor element fixed thereto, without the cap. 1... Header, 2, 12... Cathode lead,
3...Anode lead, 4...Mount base,
5...Diode pellet, 6...Thin metal wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ヘツダを貫通して設けられた一本のリードの上
端部に溶接により取り付けられた半導体素子をマ
ウントするマウントベースを有する半導体装置用
パツケージにおいて、前記リード上端部が平たん
加工され、かつ平たい面を上面として逆L字形に
曲げられ、かつ、この平たい上面に前記マウント
ベースが溶接されていることを特徴とする半導体
装置用パツケージ。
In a package for a semiconductor device having a mount base for mounting a semiconductor element attached by welding to the upper end of one lead provided through a header, the upper end of the lead is processed to be flat and has a flat surface. A package for a semiconductor device, characterized in that the upper surface is bent into an inverted L shape, and the mount base is welded to this flat upper surface.
JP16772386U 1986-10-30 1986-10-30 Pending JPS6373941U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16772386U JPS6373941U (en) 1986-10-30 1986-10-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16772386U JPS6373941U (en) 1986-10-30 1986-10-30

Publications (1)

Publication Number Publication Date
JPS6373941U true JPS6373941U (en) 1988-05-17

Family

ID=31099920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16772386U Pending JPS6373941U (en) 1986-10-30 1986-10-30

Country Status (1)

Country Link
JP (1) JPS6373941U (en)

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