JPS6373566A - Manufacture of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To control the thickness of a gate oxide film independently by depositing an insulating film, a conductive film and an oxidation-resistant film onto a semiconductor base body in succession, selectively leaving the laminated films only at a predetermined position and forming floating gate structure. CONSTITUTION:An oxide film 11 is shaped onto a P-type silicon semiconductor substrate 10, and a polycrystalline silicon film 12 is deposited onto the oxide film 11 through CVD. Laminated films 13 consisting of an oxide film, a nitride film and an oxide film are deposited onto the film 12. The oxide film 11, the silicon film 12 and the laminated films 13 are patterned and left only in a memory cell region. An oxide film 14 is shaped through a thermal oxidation method, a polycrystalline silicon film 15 is deposited on the whole surface through CVD, the gate structure of a peripheral element composed of the laminated structure of the oxide film 14 and the silicon film 15 and the floating gate structure of a memory cell are formed, and an N-type impurity is ion-implanted, using these gate structure as masks to shape regions 16. An oxide film 17 is formed while the regions 16 are activated, and the memory cell and N-type source-drain diffusion regions 18 are shaped. Accordingly, the thickness of the gate oxide films of the memory cell and the peripheral element can be controlled independently without deteriorating characteristics and reliability.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a nonvolatile semiconductor memory device using a nonvolatile element having a double gate structure consisting of a floating gate and a control gate as a memory cell. Regarding the manufacturing method.

(Prior Art) In a nonvolatile semiconductor memory device called an EPROM, which uses a nonvolatile element with a double gate structure consisting of a floating gate and a control gate as a memory cell, data is written by injecting electrons into the floating gate. Data is erased by emitting electrons previously stored in the floating gate by irradiation with ultraviolet rays.

Incidentally, conventionally, such an EPROM has been manufactured by a process as shown in the cross-sectional view of FIG. That is,
First, as shown in FIG. 2(a), a semiconductor substrate 20
After depositing a gate oxide film 21 thereon, a first layer of polycrystalline silicon $I22 as a gate electrode material is deposited, and then a second layer Ii consisting of this gate oxide film 21 and polycrystalline silicon film 22 is deposited. A hole 23 called a cell slit is opened. Next, as shown in FIG. 2(b), a laminated film 24 consisting of a three-layer structure of an oxide film, a nitride film, and an oxide film is formed on the surface.
Then, as shown in FIG. 2(C), the memory cell area is masked with a resist 25 to remove unnecessary @m film 24, polycrystalline silicon film 22, and gate oxide [121] outside the memory cell area. A floating gate structure of the memory cell is formed in the memory cell area by etching. During this etching, the laminated layer 1124 attached to the side wall of the polycrystalline silicon film 22 remains because it is thick in the vertical direction. Thereafter, gate oxidation [A2B] of the peripheral element is formed on the peripheral element region as shown in FIG. 2(d). Furthermore, as shown in FIG. 2(e), a second layer of polycrystalline silicon 27 is deposited thereon, and this polycrystalline silicon [127
and gate oxidation i! After patterning 26 to form the 1111 gate structure of the memory cell and the gate structure of the peripheral element, ion implantation is performed using the control gate structure of the memory cell and the gate structure of the peripheral element as masks to form the ion implantation region 28. . Next, as shown in FIG. 2(f), a post-oxidation film 29 is formed and at the same time the ion implantation region 1ii 128 is activated to form source and drain diffusion regions 30 of the memory cell and peripheral elements.

In this way, in the above method, gate oxidation of memory cells and peripheral elements II! Since the thickness can be controlled independently, it has the advantage that a highly versatile EPROM can be manufactured.

However, according to the above method, there is a problem in that the presence of the laminated rlA 24 remaining in the step of FIG. 2(C) has an adverse effect on subsequent steps. For example, - (when forming the on-implantation region 28, impurity ions are not sufficiently implanted into the substrate 20 below the laminated film 24, so the source in that part is removed as shown in FIG. 2(f)).

The diffusion depth of the drain diffusion region 30 becomes shallower, and the source,
Drain resistance increases. Further, there is also the problem that this laminated film 24 becomes a source of contamination and adversely affects subsequent processes.

(Problems to be Solved by the Invention) Although the conventional method has the advantage of being able to independently control the gate oxide film thickness of the memory cell and peripheral elements, it has the disadvantage that the characteristics and reliability deteriorate. There are drawbacks.

This invention was made in consideration of the above circumstances, and its purpose is to be able to independently control the gate oxide film thickness of the memory cell and peripheral elements without deteriorating the characteristics or reliability. An object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device.

[Structure of the Invention] <Means for Solving the Problems> A method for manufacturing a nonvolatile semiconductor memory device of the present invention includes the first
sequentially depositing an insulating first film, a conductive second film, and an oxidation-resistant third film on a conductive type semiconductor substrate;
forming a floating gate structure of a non-volatile element for a memory cell by selectively leaving the laminated film consisting of the first, second and third films at predetermined positions; and forming a fourth insulating film on the entire surface. and a step of sequentially depositing a conductive fifth film;
and a step of forming a gate structure of a peripheral element and a control gate structure of the nonvolatile element by selectively leaving a laminated film consisting of a fifth film only at a predetermined position.

A second conductivity type impurity is implanted into the substrate using the floating gate structure of the nonvolatile element and the gate structure of the peripheral element as a mask to form the source and drain regions of the nonvolatile element and the peripheral element, respectively. It consists of a step of forming.

(Function) In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, an insulating first film, a conductive second film, and an oxidation-resistant M3 film are sequentially formed on a first conductivity type semiconductor substrate. After the deposition, the laminated film consisting of the first, second, and third patterns is selectively left only at predetermined positions to form a floating gate structure of a nonvolatile element for a memory cell. The laminated film consisting of the third film and the third film is left only in necessary locations.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view sequentially showing manufacturing steps according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a silicon oxide film 11 with a thickness of 200 nm is formed on, for example, a P-type silicon semiconductor substrate 10, and then a silicon oxide film 11 is formed using CVD (chemical vapor deposition method).
Then a polycrystalline silicon film 1 with a thickness of 4,000 wafers is deposited on top of it.
Deposit 2. Furthermore, a laminated film 13 having a three-layer structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film is deposited thereon.

This laminated I! ! 13 is formed by sequentially depositing a silicon oxide film, a silicon nitride film, and a silicon oxide film using a well-known method.

Next, as shown in FIG. 1(b), the silicon oxide 1111, the polycrystalline silicon 1112 and the product 11WA13
is patterned using well-known photolithography and etching techniques to leave it only in the memory cell area.

Next, as shown in FIG. 1C, a silicon oxide film 14 is formed to a thickness of 250 nm on the exposed surface of the substrate 10 by thermal oxidation. At this time, the 8I film 13 left in advance
Because the silicon nitride film has wave resistance, hardly any silicon oxide film grows around it, and on the contrary, a thicker silicon oxide film grows on the sidewalls of the polycrystalline silicon film 12.

Next, as shown in FIG. 1(d), a second layer of polycrystalline silicon film 15 with a thickness of 3,500 mm is formed over the entire surface by CVD.
is deposited and further patterned using well-known photolithography and etching techniques to form a gate structure of a peripheral element and a floating gate structure of a memory cell consisting of a laminated structure of silicon oxide GL 14 and polycrystalline silicon film 15, and further Using the gate structure of the peripheral elements and the floating gate structure of the memory cell as a mask, N-type impurities such as arsenic ions (AS) are applied at 40KeVr 5x10f'/
The ion implantation region 16 is formed by ion implantation with a dose of cm3.
form.

Next, as shown in FIG. 1(e), the post-oxide film 17 is
At the same time, the ion implantation region 16 is activated by heat treatment to form the N-type source and drain diffusion regions 18 of the memory cell and peripheral elements.

According to the method of the above embodiment, after the silicon oxide film 11, the polycrystalline silicon 1112, and the V4 layer pattern 3 are sequentially deposited on the substrate 10, these deposited films are selectively left only in predetermined positions. The floating gate structure of the non-continuous element for the memory cell was formed using the above method, and this deposited film was left only in the necessary areas.This eliminates the various problems that occur when the laminated film is left in unnecessary areas as in the past. All the problems are solved, and deterioration of characteristics and reliability can be prevented. Moreover, since the gate oxide films of the memory cell and the peripheral elements, that is, the silicon oxides [11 and 14] are formed separately, the film thicknesses can be controlled independently. Therefore, the versatility of the manufactured EPROM can be increased.

In addition. It goes without saying that this invention is not limited to the embodiments described above, and that various modifications are possible.

For example, in the above embodiment, the laminated film 13 is formed by sequentially depositing a silicon oxide film, a silicon nitride film, and a silicon oxide film. It is also possible to form a three-layer stacked film by forming only a film, oxidizing the silicon nitride film at the same time during the gate oxidation step shown in FIG. 1(C), and forming a silicon oxide film thereon.

Furthermore, in the above embodiment, a P-type substrate is used as the substrate 10, and an N-channel type is formed as the memory cell and peripheral elements. Of course, it is also possible to do so.

Furthermore, during the process shown in FIG. 1(d), the first layer of polycrystalline silicon I! 1112 is exposed, and at the same time the second layer of polycrystalline silicon 115 is patterned, the source,
By patterning the first layer of polycrystalline silicon 112 in the direction perpendicular to the arrangement direction of the drain diffusion regions 18, it is also possible to form the floating gate and control gate of the memory cell in a self-aligned manner. .

[Effects of the Invention] As explained above, the present invention provides a nonvolatile semiconductor memory device in which the gate oxide film thicknesses of memory cells and peripheral elements can be independently controlled without deteriorating characteristics or reliability. A manufacturing method can be provided.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a manufacturing process according to a conventional method. 10... P-type silicon semiconductor substrate, 11... silicon oxide film, 12... eleventh polycrystalline silicon film,
13... Laminated film, 14... Silicon oxide film, 15.
...211th polycrystalline silicon film, 16... ion implantation region, 11... post-oxidation film, 18... N-type source and drain diffusion region. Applicant's agent Patent attorney Takehiko Suzue 1゜Figure 1

Claims (1)

[Claims] a step of sequentially depositing an insulating first film, a conductive second film, and an oxidation-resistant third film on a semiconductor substrate of a first conductivity type; A step of forming a floating gate structure of a non-volatile element for a memory cell by selectively leaving a laminated film consisting of a film at a predetermined position, and a step of forming a floating gate structure of a non-volatile element for a memory cell;
and a conductive fifth film, and selectively leave the laminated film consisting of the fourth and fifth films only at predetermined positions to form the gate structure of the peripheral element and the nonvolatile element. forming a control gate structure, and implanting a second conductivity type impurity into the base using the floating gate structure of the nonvolatile element and the gate structure of the peripheral element as masks, and forming the nonvolatile element and the peripheral element. 1. A method of manufacturing a nonvolatile semiconductor memory device, comprising the step of forming source and drain regions of each peripheral element.