JPS6371728A - 演算処理装置および演算処理方法 - Google Patents

演算処理装置および演算処理方法

Info

Publication number
JPS6371728A
JPS6371728A JP61216591A JP21659186A JPS6371728A JP S6371728 A JPS6371728 A JP S6371728A JP 61216591 A JP61216591 A JP 61216591A JP 21659186 A JP21659186 A JP 21659186A JP S6371728 A JPS6371728 A JP S6371728A
Authority
JP
Japan
Prior art keywords
digit
multiplier
binary
group
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61216591A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0582608B2 (enrdf_load_stackoverflow
Inventor
Tadashi Takagi
高木　直史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61216591A priority Critical patent/JPS6371728A/ja
Priority to US07/095,525 priority patent/US4868777A/en
Publication of JPS6371728A publication Critical patent/JPS6371728A/ja
Priority to US07/599,275 priority patent/US5153847A/en
Publication of JPH0582608B2 publication Critical patent/JPH0582608B2/ja
Granted legal-status Critical Current

Links

JP61216591A 1986-06-27 1986-09-12 演算処理装置および演算処理方法 Granted JPS6371728A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61216591A JPS6371728A (ja) 1986-09-12 1986-09-12 演算処理装置および演算処理方法
US07/095,525 US4868777A (en) 1986-09-12 1987-09-10 High speed multiplier utilizing signed-digit and carry-save operands
US07/599,275 US5153847A (en) 1986-06-27 1990-10-16 Arithmetic processor using signed digit representation of internal operands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61216591A JPS6371728A (ja) 1986-09-12 1986-09-12 演算処理装置および演算処理方法

Publications (2)

Publication Number Publication Date
JPS6371728A true JPS6371728A (ja) 1988-04-01
JPH0582608B2 JPH0582608B2 (enrdf_load_stackoverflow) 1993-11-19

Family

ID=16690816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61216591A Granted JPS6371728A (ja) 1986-06-27 1986-09-12 演算処理装置および演算処理方法

Country Status (1)

Country Link
JP (1) JPS6371728A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02148326A (ja) * 1988-11-30 1990-06-07 Nec Corp 乗算器
JPH0511981A (ja) * 1990-08-07 1993-01-22 Matsushita Electric Ind Co Ltd 乗算処理装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02148326A (ja) * 1988-11-30 1990-06-07 Nec Corp 乗算器
JPH0511981A (ja) * 1990-08-07 1993-01-22 Matsushita Electric Ind Co Ltd 乗算処理装置

Also Published As

Publication number Publication date
JPH0582608B2 (enrdf_load_stackoverflow) 1993-11-19

Similar Documents

Publication Publication Date Title
US6393454B1 (en) Booth multiplier with low power, high performance input circuitry
Verma Design of 4x4 bit vedic multiplier using EDA tool
JPH02196328A (ja) 浮動小数点演算装置
US4868777A (en) High speed multiplier utilizing signed-digit and carry-save operands
Timarchi et al. Arithmetic circuits of redundant SUT-RNS
Yan et al. An energy-efficient multiplier with fully overlapped partial products reduction and final addition
Jaberipur et al. Unified Approach to the Design of Modulo-(2^ n+/-1) Adders Based on Signed-LSB Representation of Residues
JPH03116326A (ja) 高速並列乗算器回路
JPS60179840A (ja) 加算器
Timarchi et al. A novel high-speed low-power binary signed-digit adder
JP2001501341A (ja) デジタル加算器回路
JPS6371728A (ja) 演算処理装置および演算処理方法
Liao et al. A carry-select-adder optimization technique for high-performance booth-encoded wallace-tree multipliers
US4935892A (en) Divider and arithmetic processing units using signed digit operands
Lavanya et al. Design and implementation of Vedic multiplier using carry increment adder
JP2682142B2 (ja) 乗算装置
Vinoth et al. Design and Implementation of High Speed 32-bit MAC Unit
JPH0610787B2 (ja) 乗算処理装置
JPH0528407B2 (enrdf_load_stackoverflow)
Lv et al. Efficient diminished-1 modulo 2 n+ 1 multiplier architectures
Großschadl A unified radix-4 partial product generator for integers and binary polynomials
JPH0652500B2 (ja) 演算処理装置
Sahu et al. Improved redundant binary adder realization in FPGA
JP2563473B2 (ja) ２進演算器
JPH0582609B2 (enrdf_load_stackoverflow)

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term