JPS636871A - Charge transfer type solid image sensing element - Google Patents
Charge transfer type solid image sensing elementInfo
- Publication number
- JPS636871A JPS636871A JP61150801A JP15080186A JPS636871A JP S636871 A JPS636871 A JP S636871A JP 61150801 A JP61150801 A JP 61150801A JP 15080186 A JP15080186 A JP 15080186A JP S636871 A JPS636871 A JP S636871A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- charge transfer
- vertical shift
- horizontal shift
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title 1
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000003384 imaging method Methods 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 230000002950 deficient Effects 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電荷転送型固体撮像素子に関し、特に埋込みチ
ャネル型電荷転送素子からなる垂直シフトレジスタと水
平シフトレジスタを含む電荷転送型固体撮像素子に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer type solid-state image sensor, and more particularly to a charge transfer type solid-state image sensor including a vertical shift register and a horizontal shift register comprising a buried channel type charge transfer element. .
電荷転送型の固体撮像素子では、信号電荷を光電変換素
子から垂直シフトレジスタに読み出し、垂直シフトレジ
スタから水平シフトレジスタに転送した後に、水平シフ
トレジスタにより出力用の増幅器に転送して、撮像信号
を得ている。この際水平シフトレジスタで信号電荷を転
送時、水平シフトレジスタから垂直シフトレジスタへ信
号電荷が流れ込むと、信号の転送が不完全となる。この
水平シフトレジスタでの信号電荷の転送不良の発生な防
ぐなめには、最大信号電荷を転送時の水平シフトレジス
タ電極下のチャネル電位よりも、垂直シフトしジスタの
水平シフトレジスタへの接続部すなわち垂直ジフトレジ
スタの出口の電位を低くする必要がある。通常電荷転送
型固体撮像素子では信号電荷の高速転送を行なうために
水平シフトレジスタには２相駆動ＣＣＤが使用されてい
る。２相駆動ＣＣＤでは転送電極は電荷を蓄えるストレ
ージ部と電荷の逆流を防ぐバリア部とから成り、最大信
号電荷量はストレージ部とバリア部の空乏電位の差によ
って決まり、最大信号電荷を転送時の水平シフトレジス
タ電極下の電位は、バリア部の電位と等しい。したがっ
て、このバリア部の電位よりも垂直シフトレジスタの出
口の電位を低くすれば、水平シフトレジスタから垂直シ
フトレジスタへの信号電荷の流れ込みによる水平シフト
レジスタでの信号電荷の転送不良は発生しない。In a charge transfer solid-state imaging device, the signal charge is read out from the photoelectric conversion element to the vertical shift register, transferred from the vertical shift register to the horizontal shift register, and then transferred to the output amplifier by the horizontal shift register to convert the image signal. It has gained. At this time, when signal charges are transferred by the horizontal shift register, if the signal charges flow from the horizontal shift register to the vertical shift register, the signal transfer will be incomplete. In order to prevent signal charge transfer failure in this horizontal shift register, the maximum signal charge is shifted vertically from the channel potential under the horizontal shift register electrode at the time of transfer, and the junction of the register to the horizontal shift register, It is necessary to lower the potential at the exit of the vertical shift resistor. Generally, in a charge transfer type solid-state image pickup device, a two-phase drive CCD is used as a horizontal shift register in order to transfer signal charges at high speed. In a two-phase drive CCD, the transfer electrode consists of a storage part that stores charge and a barrier part that prevents reverse flow of charge.The maximum signal charge amount is determined by the difference in depletion potential between the storage part and the barrier part, and the maximum signal charge is The potential under the horizontal shift register electrode is equal to the potential at the barrier section. Therefore, if the potential at the exit of the vertical shift register is set lower than the potential at the barrier portion, a signal charge transfer failure in the horizontal shift register due to the flow of signal charges from the horizontal shift register to the vertical shift register will not occur.
従来の電荷転送型固体撮像素子では、垂直シフトレジス
タと水平シフトレジスタは同一のイオン注入工程により
形成されておりチャネル領域の不純物濃度は等しくなっ
ているため、垂直シフトレジスタをそのまま水平シフト
レジスタに接続すると垂直シフトレジスタの出口の電位
は水平シフトレジスタのバリア部の電位よりも高くなっ
てしまう。そこで従来は垂直シフトレジスタの出口でチ
ャネル幅を細く絞り込むことで、侠チャネル効果を利用
して、垂直シフトレジスタの出口の電位を水平シフトレ
ジスタのバリア部の電位よりも低くすることによって、
水平シフトレジスタでの信号電荷の転送不良の発生を防
いでいる。In conventional charge transfer solid-state imaging devices, the vertical shift register and horizontal shift register are formed by the same ion implantation process, and the impurity concentration in the channel region is the same, so the vertical shift register can be directly connected to the horizontal shift register. Then, the potential at the exit of the vertical shift register becomes higher than the potential at the barrier section of the horizontal shift register. Therefore, conventionally, by narrowing the channel width at the exit of the vertical shift register and making use of the chivalrous channel effect, the potential at the exit of the vertical shift register is made lower than the potential at the barrier section of the horizontal shift register.
This prevents signal charge transfer failures in the horizontal shift register.
第４図は従来の電荷転送型固体撮像素子の垂直シフトレ
ジスタと水平シフトレジスタの接続部を示す平面図であ
る。チャネルストップ領域１−１．１−２により、垂直
シフトレジスタ５および水平シフトレジスタ６を規定し
ており垂直シフトレジスタの水平シフトレジスタへの接
続部は幅が狭く絞り込まれている。転送電極は第１層目
の多結晶シリコン電極２および第２層目の多結晶シリコ
ン電極３−１から成る。水平シフトレジスタ６は第１層
目の多結晶シリコン電極２下を２相駆動ＣＣＤのストレ
ージ部とし、第２層目の多結晶シリコン電極３−１を形
成する前に第１層目の多結晶シリコン電極２をマスクに
して不純物をイオン注入することにより、第２層目の多
結晶シリコン電極３−１下の空乏電位を第１層目の多結
晶シリコン電極２下すなわちストレージ部の請乏電位よ
りも低くして２相駆動ＣＣＤのバリア部を形成している
。FIG. 4 is a plan view showing a connection portion between a vertical shift register and a horizontal shift register of a conventional charge transfer solid-state image sensor. The channel stop region 1-1.1-2 defines a vertical shift register 5 and a horizontal shift register 6, and the connection portion of the vertical shift register to the horizontal shift register is narrowed in width. The transfer electrode consists of a first layer polycrystalline silicon electrode 2 and a second layer polycrystalline silicon electrode 3-1. The horizontal shift register 6 uses the area under the first layer of polycrystalline silicon electrode 2 as a storage section for a two-phase drive CCD, and before forming the second layer of polycrystalline silicon electrode 3-1, the first layer of polycrystalline silicon electrode 2 is By ion-implanting impurities using the silicon electrode 2 as a mask, the depletion potential under the second layer polycrystalline silicon electrode 3-1 becomes the depletion potential under the first layer polycrystalline silicon electrode 2, that is, the storage area. The barrier portion of the two-phase drive CCD is formed by lowering the barrier portion.
第５図（ａ＞、（ｂ）はそれぞれ第４図のＡ−Ａ′線及
びＢ−Ｂ’線に沿った電位分布図であり垂直シフトレジ
スタ側の第２層目の多結晶シリコン電極３−２に印加す
るクロック電圧φｌをオフ、水平レジスタ側の第１層目
の多結晶シリコン電極２に印加するクロック電圧φ２を
オンにする事により電荷の転送を行う時のものである。FIGS. 5(a) and 5(b) are potential distribution diagrams along lines A-A' and B-B' in FIG. 4, respectively, showing the second layer polycrystalline silicon electrode 3 on the vertical shift register side. This is when charge transfer is performed by turning off the clock voltage φl applied to the -2 and turning on the clock voltage φ2 applied to the first layer polycrystalline silicon electrode 2 on the horizontal register side.
垂直シフトレジスタの出口の電位２１はこの分布のチャ
ネル幅を狭く絞り込むことによって水平シフトレジスタ
のバリア部の電位２０より低くしである。従って転送不
良は発生しないはずである。The potential 21 at the exit of the vertical shift register is made lower than the potential 20 at the barrier portion of the horizontal shift register by narrowing the channel width of this distribution. Therefore, no transfer failure should occur.
しかし、垂直シフトレジスタの出口の部分において、狭
チャネル効果で生じたバリア２２が存在し、新たな転送
不良が生じてしまう。However, at the exit of the vertical shift register, there is a barrier 22 caused by the narrow channel effect, resulting in a new transfer failure.
上述した従来の電荷転送型固体撮像素子は、垂直シフト
レジスタへの接続部を狭くしているので、垂直シフトレ
ジスタの幅を絞り込む部分で、狭チャネル効果で生じた
バリアにより、垂直シフトレジスタの出口において信号
電荷の転送不良が発生し易いという欠点がある。In the conventional charge transfer type solid-state image sensor described above, the connection part to the vertical shift register is narrowed, so in the part where the width of the vertical shift register is narrowed, the exit of the vertical shift register is blocked by the barrier created by the narrow channel effect. The disadvantage is that signal charge transfer failures are likely to occur.
本発明の目的は、転送不良のない電荷転送型固体撮像素
子を提供することにある。An object of the present invention is to provide a charge transfer type solid-state image sensor without transfer defects.
本発明の電荷転送型固体撮像素子は、２次元的に配列さ
れた光電変換素子群、該光電変換素子群からの光信号電
荷を垂直方向に転送する埋込みチャネル型電荷転送素子
からなる垂直シフトレジスタ群と、該垂直シフトレジス
タ群に接続され該光信号電荷を水平方向に転送する埋込
みチャネル型電荷転送素子からなる水平シフトレジスタ
群を有してなる電荷転送型固体撮像素子において、該水
平シフトレジスタ群の埋込みチャネルを形成する不純物
濃度を該垂直シフトレジスタ群の埋込みチャネルを形成
する不純物濃度よりも大きくしたものである。The charge transfer solid-state imaging device of the present invention includes a vertical shift register comprising a group of two-dimensionally arranged photoelectric conversion elements and a buried channel charge transfer element that vertically transfers optical signal charges from the group of photoelectric conversion elements. and a horizontal shift register group consisting of a buried channel charge transfer element connected to the vertical shift register group and horizontally transferring the optical signal charge, the horizontal shift register The impurity concentration forming the buried channels of the group is set higher than the impurity concentration forming the buried channels of the vertical shift register group.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の主要部を示す半導体チップ
の平面図であり、垂直シフトレジスタと水平シフトレジ
スタの接続部が図示しである。第２図（ａ＞、（ｂ）は
それぞれ第１図のＡ−Ａ’’断面図及びＢ−Ｂ’’断面
図である。Ｐ“型のチャネルストップ領域１−１．１−
２で垂直シフトレジスタ５および水平シフトレジスタ６
の幅を規定しており本発明においては、垂直シフトレジ
スタ５の幅は一定であり水平シフトレジスタ６に接続す
る部分でのチャネル幅の絞り込みは行なっていない。チ
ャネルストップ領域１−１．１−２を形成した後垂直シ
フトレジスタ５および水平シフトレジスタ６にチャネル
を形成するための第１回目のイオン注入を行ない、次に
レジストをマスクに第２のイオン注入領域４に第２回目
のイオン注入を行なうことにより、水平シフトレジスタ
６を形成するチャネル領域の不純物濃度を、垂直シフト
レジスタ５を形成するチャネル領域の不純物濃度よりも
高くする。同図において２は第１層目の多結晶シリコン
電極、：３−１．３−２は第２層目の多結晶シリコン電
極であり、水平シフトレジスタ６には第１層目の多結晶
シリコン電極２をマスクにして２相駆動ＣＣＤのバリア
部を形成するためのイオン注入を行う。FIG. 1 is a plan view of a semiconductor chip showing the main parts of an embodiment of the present invention, in which a connecting portion between a vertical shift register and a horizontal shift register is illustrated. FIGS. 2(a) and 2(b) are a cross-sectional view taken along the line AA'' and a cross-sectional view taken along the line B-B'' in FIG. 1, respectively. P" type channel stop region 1-1.1-
2 to vertical shift register 5 and horizontal shift register 6
In the present invention, the width of the vertical shift register 5 is constant, and the channel width at the portion connected to the horizontal shift register 6 is not narrowed down. After forming channel stop regions 1-1, 1-2, a first ion implantation is performed to form channels in the vertical shift register 5 and horizontal shift register 6, and then a second ion implantation is performed using the resist as a mask. By performing the second ion implantation into region 4, the impurity concentration of the channel region forming horizontal shift register 6 is made higher than the impurity concentration of the channel region forming vertical shift register 5. In the figure, 2 is the first layer polycrystalline silicon electrode, 3-1.3-2 is the second layer polycrystalline silicon electrode, and the horizontal shift register 6 is the first layer polycrystalline silicon electrode. Using electrode 2 as a mask, ion implantation is performed to form a barrier portion of a two-phase drive CCD.
第３図（ａ）、（ｂ）はそれぞれ第２図（ａ）。Figures 3(a) and (b) are respectively Figure 2(a).
（ｂ）に示す電極配置に沿った電位分布図であり、垂直
シフトレジスタ側の第２層目の多結晶シリコン電極３−
２に印加するクロック電圧φ１をオフ、水平シフトレジ
スタ側の第１層目の多結晶シリコン電極２に印加するク
ロック電圧φ２をオンにする事により電荷の転送を行う
時のものである。水平シフトレジスタ部の電位すなわち
２相駆動ＣＣＤのバリア部の電位２０が垂直シフトレジ
スタの出口の電位２１よりも高くなる様に第２のイオン
注入領域４に不純物のイオン注入が行なわれているわけ
である。It is a potential distribution diagram along the electrode arrangement shown in (b), and is a polycrystalline silicon electrode 3- of the second layer on the vertical shift register side.
This is when charge transfer is performed by turning off the clock voltage φ1 applied to the first layer polycrystalline silicon electrode 2 on the horizontal shift register side and turning on the clock voltage φ2 applied to the first layer polycrystalline silicon electrode 2 on the horizontal shift register side. Impurity ions are implanted into the second ion implantation region 4 so that the potential of the horizontal shift register section, that is, the potential 20 of the barrier section of the two-phase drive CCD, is higher than the potential 21 of the exit of the vertical shift register. It is.
以上説明したように本発明は電荷転送型固体撮像素子に
おいて、水平シフトレジスタを形成するチャネル領域の
不純物濃度を垂直シフトレジスタを形成するチャネル領
域の不純物濃度よりも高くし、水平シフトレジスタの空
乏電位を垂直シフトレジスタの空乏電位よりも、従来垂
直シフトレジスタの出口のチャネル幅を絞ることで、狭
チャネル効果を利用していた電位差分だけ高くすること
により、垂直シフトレジスタの出口を絞り込む必要を無
くしたもので、垂直シフトレジスタの出口での信号電荷
の転送不良発生を防止できる。As explained above, the present invention provides a charge transfer type solid-state imaging device in which the impurity concentration of the channel region forming the horizontal shift register is made higher than the impurity concentration of the channel region forming the vertical shift register, and the depletion potential of the horizontal shift register is By narrowing the channel width at the exit of the conventional vertical shift register, the narrow channel effect is made higher than the depletion potential of the vertical shift register by the potential difference, eliminating the need to narrow the exit of the vertical shift register. This can prevent signal charge transfer failures at the exit of the vertical shift register.
なお本発明は水平シフトレジスタに２相駆動ＣＣＤ以外
の方式のＣＣＤを使用した場合についても同様の効果が
あることは勿論である。It goes without saying that the present invention has similar effects even when a CCD of a type other than the two-phase drive CCD is used in the horizontal shift register.
【図面の簡単な説明】
第１図は本発明の一実施例の主要部を示す半導体チップ
の平面図、第２図（ａ）、（ｂ）はそれぞれ第１図のＡ
−Ａ’’断面図及びＢ−Ｂ’線線面面図第３図＜ａ＞、
（ｂ）はそれぞれ第２図（ａ＞、（ｂ）に示す電極配置
に沿った電位分布図、第４図は従来例の主要部を示す半
導体チップの平面図、第５図（ａ）、（ｂ）はそれぞれ
第４図のＡ−Ａ′線及びＢ−Ｂ′線に沿った電位分布図
である。
１−１．１−２・・・チャネルストップ領域、２・・・
第１層目の多結晶シリコン電極、３−１．３−２・・・
第２層目の多結晶シリコン電極、４・・・第２のイオン
注入領域、５・・・垂直シフトレジスタ、６・・・水平
シフトレジスタ、７・・・ｐ型半導体基板、８・・・Ｓ
ｉ ０２膜、９・・・第１のイオン注入領域。
／−／、１４ チャネルスト・ノブ々負ｄ（２Ｖ１１
層日のｉＫ品シリコン社１（
３−ｔ、ｓ−ｚ 第ｅｓ巨のタオ台晶シリコン電オ（
４局〜２’／）イオ：−；ｉ？４域
３１島亘シフトＬ−シ゛又り、６−Ｐｋ−ｙシフトレジ
ブタ（λ）
猶 ３ 区
／−／、 ／−２’ 少マイル又ト・ノブ鎖酸Ｚ 項
％ｔ４＠ｎり、桔品ラリフンにキ吸３−ｔ、３−ｚ
＃２層＠／７タ、ｉＦａ ；’） ：Ｉ ンＬＦｉｉ−
、ｓ 立しシフトレジ′°又夕、６ メ（千三フトレシ
″又りめ４ 図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view of a semiconductor chip showing the main parts of an embodiment of the present invention, and FIGS. 2(a) and 2(b) are A of FIG.
-A'' sectional view and B-B' line plane view Figure 3 <a>,
(b) is a potential distribution diagram along the electrode arrangement shown in FIGS. 2(a> and (b)), FIG. 4 is a plan view of a semiconductor chip showing the main parts of the conventional example, and FIG. 5(a), (b) is a potential distribution diagram along the A-A' line and the B-B' line in Fig. 4, respectively. 1-1.1-2...Channel stop region, 2...
First layer polycrystalline silicon electrode, 3-1.3-2...
Second layer polycrystalline silicon electrode, 4... Second ion implantation region, 5... Vertical shift register, 6... Horizontal shift register, 7... P-type semiconductor substrate, 8... S
i02 film, 9...first ion implantation region. /-/, 14 Channel strike knobs negative d (2V11
Layer day's iK products silicon company 1 (3-t, s-z esth es giant Taodai crystal silicon electronics company (3-t, s-z)
4th station~2'/) Io:-;i? 4 area 31 island shift L-shape, 6-Pky shift resistor (λ) Rarifun Ki Sucking 3-t, 3-z
#2 layer @/7 ta, iFa;'):I LFii-
, s Standing shift register '° Matarime, 6 Me (1300 shift register ' Matarime 4 Figure
Claims (1)
群からの光信号電荷を垂直方向に転送する埋込みチャネ
ル型電荷転送素子からなる垂直シフトレジスタ群と、該
垂直シフトレジスタ群に接続され該光信号電荷を水平方
向に転送する埋込みチャネル型電荷転送素子からなる水
平シフトレジスタ群を有してなる電荷転送型固体撮像素
子において、該水平シフトレジスタ群の埋込みチャネル
を形成する不純物濃度は該垂直シフトレジスタ群の埋込
みチャネルを形成する不純物濃度よりも大きいことを特
徴とする電荷転送型固体撮像素子。A group of photoelectric conversion elements arranged two-dimensionally, a vertical shift register group consisting of a buried channel charge transfer element that vertically transfers optical signal charges from the photoelectric conversion element group, and a group of vertical shift registers connected to the vertical shift register group. In a charge transfer type solid-state image sensing device having a horizontal shift register group consisting of a buried channel type charge transfer element that horizontally transfers the optical signal charge, the impurity concentration forming the buried channel of the horizontal shift register group is as follows. A charge transfer solid-state imaging device characterized in that the impurity concentration is higher than the impurity concentration forming the buried channels of the vertical shift register group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150801A JPS636871A (en) | 1986-06-26 | 1986-06-26 | Charge transfer type solid image sensing element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150801A JPS636871A (en) | 1986-06-26 | 1986-06-26 | Charge transfer type solid image sensing element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS636871A true JPS636871A (en) | 1988-01-12 |
Family
ID=15504724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61150801A Pending JPS636871A (en) | 1986-06-26 | 1986-06-26 | Charge transfer type solid image sensing element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS636871A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0296730U (en) * | 1989-01-18 | 1990-08-01 |
-
1986
- 1986-06-26 JP JP61150801A patent/JPS636871A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0296730U (en) * | 1989-01-18 | 1990-08-01 |
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