JPH0319349A - Charge-coupled device - Google Patents

Abstract

PURPOSE:To dispense with a polycrystalline silicon gate to a transistor for load use and a wiring to the gate by a method wherein the transistor for load use of the charge detecting circuit of a CCD having a virtual gate charge transfer part is formed as a junction type and is formed simultaneously with the virtual gate charge transfer part. CONSTITUTION:An N-type well 16 is formed by implanting ions and after that, an N-type impurity 7 is ion-implanted to form a potential well region 2 and channel regions of transistors 18 and 19 and a P-type impurity 6 is ion-implanted on them to form simultaneously a virtual gate region 5 and gate regions 10 and 11 of the transistors 18 and 19. At this time, the respective regions result in being set automatically in an earth potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge-coupled device, and in particular to the ellipse of a charge detection section disposed at the final stage thereof.

[Prior Art] Charge-coupled devices (hereinafter abbreviated as CCD) are currently widely used for solid-state imaging devices, memories, filters, etc. Figure 4 shows frame interline transfer using a CCD. 1 is an overall configuration diagram of a solid-state image sensor according to the method. In this solid-state image sensor, photoelectric conversion charges generated within a light receiving section 4l are temporarily accumulated in a charge storage section 42 via a vertical CCD provided within the light receiving section. Thereafter, each horizontal video signal is transferred in parallel to the horizontal CCD section 43 and outputted from the output section 44 via this CCD section.

FIG. 5 is a sectional view of the vicinity of the output section 44 of the horizontal CCD section 43 in FIG. 4, and this CCD has a virtual gate charge transfer section and a single-phase gate charge transfer section. In FIG. 5, a p-well 14 is formed on the surface of an n-type semiconductor substrate 15, and an n-well 16 is further formed on the surface of the p-well 14 over the entire illustrated area. 1
7 is a depletion type n-channel MOS} transistor used as a reset transistor,
Floating region 16a. It has an n-type diffusion region l2 and a gate electrode 9. This n-type diffusion region 12 is connected to the power source V. ).

Further, a reset pulse φλ is applied to the gate electrode 9 at regular intervals to reset the potential of the floating region 16a. 18a and 19a are depletion type n-channel MOS transistors used as load transistors, and each has a gate voltage %10a, lla, and an n-type diffusion region 12 used as a source/drain region. MOS}
- N-type impurity 7 is ion-implanted shallowly into the channel regions of transistors 18a and 19a. The source regions of MOS transistors 18a and 19a are connected to their gate electrodes 10.
It is grounded along with a and lla. 5 is a temporary gate region formed by doping p-type impurity 6 on the surface of the n-well 16, and this region is connected to the p-well 14 through a p-type diffusion layer serving as a channel stopper.
and is fixed at ground potential. Below this area,
A potential barrier region 1 doped with n-type impurity 7 and a potential well region 2 doped with more n-type impurity 7 than this region are formed as a virtual gate charge transfer section.
Reference numeral 8 denotes a single-phase gate electrode to which a single-phase clock is applied, and a semiconductor region under this electrode is a potential barrier region 3 in which an n-well is used as is so as to constitute a single-phase gate charge transfer section. and a potential well region 4 into which n-type impurity 7 is implanted. Since the n-type impurity 7 in the potential well region 4 is doped at the same time as the impurity in the channel portions of the transistors 18a and 19a, each of these regions has the same impurity profile. 6 is a potential distribution diagram from region 1 to region l6a in FIG. 5, and FIG. 7 is a circuit diagram of the charge detection circuit. In FIG. 7, transistors 17 and 18a
．． 19a is a transistor corresponding to the transistor shown in FIG. 5, and transistors 20 and 21 are enhancement type driving MOS transistors (not shown in FIG. 5). Assuming that a high-level voltage is now applied to the single-phase gate electrode 8, the potential distribution of the charge transfer path will be as shown by the solid line in FIG. In this state, potential barrier region 1
The signal charges transferred to the area 2 and 3 pass through the areas 2 and 3 and are MWed into the potential well area 4. Next, when the voltage applied to the single-phase gate electrode 8 becomes low level, the potential under this electrode becomes as shown by the broken line in FIG.
The signal charges in the floating region 16a are transferred to the floating region 16a. As a result, the potential of the floating region 16a changes. This potential change is detected by the potential detection circuit shown in Figure 7. Thereafter, the potential of the floating region 16a is changed to the reset pulse φ applied to the gate electrode 9.
It is reset by 8. [Problems to be Solved by the Invention] In the conventional CCD described above, the load transistor in the charge detection circuit is a MOS type, and requires wiring for connecting the gate electrode to the ground potential. This gate electrode is formed of polysilicon, but its patterning is done using the wet I method, which tends to cause variations in shape.As a result, the resistance value of the load resistor of the charge detection circuit varies, resulting in uniform output characteristics. do not become. moreover,
Since many steps are required to form wiring after forming the gate, there are many chances that the polysilicon gate will be damaged and the yield will decrease.

Further, since a space for wiring is required, this becomes an obstacle to increasing the density.

[Means for Solving the Problems] The charge-coupled device of the present invention includes a virtual gate charge transfer section, a single-phase charge transfer section that receives charge from the virtual gate charge transfer section, and a single-phase gate charge transfer section. The device includes a floating region that receives charge transfer from the floating region and a charge detection circuit that detects the potential of the floating region, and the load transistor of the charge detection circuit has an impurity profile similar to that of the virtual gate charge transfer section. It is formed by a junction field effect transistor with . [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of the vicinity of the output section of a CCD showing an embodiment of the present invention. In this figure, parts that are the same as those in the conventional example shown in FIG. 5 are given the same reference numerals, so redundant explanation will be omitted. In this embodiment, junction field effect transistors 18 and 19 are used as load transistors, and the gate region and channel region of these transistors are simultaneously connected to the virtual gate region 5 and the potential well region 2 below it. It is formed. That is, n-well 16
, the dose amount is 3. OX1012/cot is formed by ion implantation at an acceleration energy of 70 keV, and then an n-type impurity 7 is added at a dose of 3. Ion implantation was performed at OX10"/CII+ and acceleration energy of 70 keV to form potential well region 2.
and channel regions of transistors 18 and 19 are formed, and p-type impurity 6 is added thereon at a dose of 1. O X I O
13/Gil! , acceleration energy 1 5 k e
Virtual gate region 5 and gate regions 10 and 11 of transistors 18 and 19 are simultaneously formed by ion implantation at V. At this time, each gate region, like the virtual gate region, is connected to the channel stopper on the other side of the paper and on this side, so each gate region is automatically set to the ground potential. Figure 2 shows an equivalent circuit diagram of the charge detection section of the device shown in Figure 1. According to this embodiment, the steps of forming a polysilicon gate and forming wiring for this gate are not necessary.
Variations in characteristics due to the use of polysilicon are eliminated, and defects caused by the wiring process are prevented, so devices with stable characteristics can be manufactured at a high yield. FIG. 3 is a sectional view showing another embodiment of the present invention. This embodiment differs from the previous embodiments in that the load junction field effect transistor 18 is formed at the same time as the potential barrier region 1 of the virtual gate charge transfer section. That is, the n-type impurity 7 is added at a dose of 2. ○x l Q l
2/c, these regions are formed simultaneously by ion implantation at an acceleration energy of 70 keV. According to this embodiment, the capacitance of the first-stage n-channel junction transistor 18 can be reduced. [Effects of the Invention] As explained above, in the present invention, the load transistor of a CCD charge detection circuit having a virtual gate charge transfer section is formed as a junction type at the same time as the virtual gate charge transfer section. According to the invention, there is no need for a polysilicon gate for a load transistor and wiring therefor. Therefore, according to the present invention, it is possible to suppress variations in characteristics due to the use of polysilicon gates, and it is possible to prevent defects caused by forming wiring for polysilicon gates. In addition, the ability to omit wiring simplifies device design.
This makes it possible to increase the density of devices.

[Brief explanation of the drawing]

Claims (1)

[Claims] a virtual gate charge transfer section having a second conductivity type region on a surface formed in the first conductivity type well; a floating region provided in the first conductivity type well after the virtual gate charge transfer section; a single-phase gate charge transfer section having a single-phase gate that controls charge transfer from the virtual gate charge transfer section to the floating region; and a charge detection circuit that detects the potential of the floating region and includes a drive transistor and a load transistor. In the charge-coupled device, the load transistor is constituted by a junction field effect transistor whose gate is a second conductivity type region formed on the surface of the first conductivity type well. Coupling element.