JPH0230189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device with reduced afterimage and a method for driving the same.

Among solid-state imaging devices, charge-coupled devices (CCDs)
Solid-state imaging devices using 3D have low output capacitance, have low noise, and can perform imaging at extremely low illuminance. However, for example, in a conventional interline transfer type CCD solid-state imaging device using a pn junction as a storage region, the afterimage becomes more noticeable as the illumination becomes lower, and the reproduced image becomes unwatchable. Therefore, instead of noise determining the low-light imaging limit, the afterimage determines the low-light imaging limit. By reducing afterimages, the limit illuminance that can be captured can be lowered.

FIG. 1 is a schematic plan view of an interline transfer type CCD secondary solid-state imaging device using a pn junction as a storage region. A large number of n-type storage regions 1 are formed in a plurality of rows on the main surface of a p-type semiconductor substrate on the light-receiving side, making pn junctions with the substrate and storing signal charges caused by incident light. Vertical CCD registers 2 as signal charge transfer means are formed adjacent to and corresponding to each column of the storage region 1. Perpendicular to accumulation area 1
A transfer gate 3 is provided between the CCD register 2 and the CCD register 2 . One end of the vertical CCD register 2 is connected to a horizontal CCD register 4, and one end of the horizontal CCD register 4 is connected to an output device 5. Portions other than the storage region 1 where photoelectric conversion is performed are shielded from light by aluminum.

The driving method and operation of such an interline transfer type CCD two-dimensional image sensor will be explained.

During signal charge accumulation, signal charges are accumulated in the accumulation region 1 in response to incident light. This signal charge is transferred to the vertical CCD register 2 by turning on the transfer gate 3 and forming a channel. When transfer gate 3 turns off and there is no channel, vertical CCD register 2
A potential barrier is formed between the storage region 1 and the storage region 1, and the next storage of signal charges begins. Vertical CCD register 2 and horizontal CCD register 4 are driven by pulses,
The signal charge transferred to vertical CCD register 2 is vertical
Transfer to the end of CCD register 2, and then horizontally
It is transferred to the output device 5 through the CCD register 4.

FIG. 4 is a diagram showing a cross section along the - line of the CCD two-dimensional solid-state imaging device shown in FIG. 1 and the potential distribution in each region. Further, the same areas as in FIG. 1 are indicated by the same symbols. An n-type storage region 1, a vertical CCD register 2, and a transfer gate region 3, which constitute a single cell, are formed on a p-type substrate 6. 12
1 is a transfer gate electrode, and 13 is a transfer electrode of a vertical CCD, which is formed on the main surface of the substrate 6 with an insulating layer 14 such as a silicon dioxide film interposed therebetween.

Next, the cause of the afterimage will be explained. Let V _A be the potential of the n-type storage region 1 with reference to the Fermi potential 15 inside the p-type substrate, and V _ch be the channel potential when the transfer gate 3 is in the on state. This V _A
is the reverse bias voltage between the p-type substrate 6 and the n-type storage region 1. Also, transfer gate 3
Let V _F be the difference between the intrinsic Fermi potential and the Fermi potential when the channel part is electrically neutral. Then, V _F is expressed as V _F =kT/q|lnN _B /ni|. Here, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _B is the impurity concentration in the channel portion, and ni is the intrinsic concentration. The V _A required to completely deplete the n-type accumulation region 1 is V _DEP
shall be. In conventional solid-state imaging devices, the donor density in storage region 1 is large, ranging from 10 ¹⁷ cells cm ³ to 10 ²¹ cells cm ³ , and V _DEP
is much larger than normal integrated circuit operating conditions.
Normally, the maximum voltage of a MOS integrated circuit is determined by the breakdown voltage of the p-n junction and the breakdown voltage of the gate oxide film.
It is 30V. During signal charge accumulation, electrons, which are signal charges, are accumulated in the accumulation region 1 in response to incident light, the depletion layer in the accumulation region 1 becomes smaller, and V _A becomes smaller as shown by curve 16. When the transfer gate 3 turns on and the channel potential reaches V _ch , signal charges begin to transfer from the storage region 1 to the vertical CCD register 2 . transfer gate 3
It is regarded as a MOS field effect transistor (MOSFET), with the storage region 1 as the source and the vertical CCD resistor 2 as the drain. Then V _A ＜V _ch ＜−
At 2V _F , this MOSFET operates in a strong inversion state,
Charge transfer occurs quickly, and V _A becomes V _ch −2V _F
It will be about. However, when V _A > V _ch −2V _F, this
Since the MOSFET operates in a weakly inverted state, charge transfer is slow, and V _A does not easily reach the final potential, V _ch - V _F. Transfer gate 3 is turned on during the vertical retrace period. This is the first part of the period. In the standard television system, the vertical retrace period is about 1110 μsec, and the period during which the transfer gate 3 is turned on is usually from about 1 μsec to about 500 μsec. For example, if the channel length of the transfer gate 3 is 5 μm, the channel width is 5 μm, and the capacitance of the storage region 1 is 0.03 pF, the time required for V _A to change from approximately V _ch −2V _F to V _ch −V _F is several times. 10 msec
, which is much larger than the period during which the transfer gate 3 is in the on state. Therefore, during the normal period when the transfer gate 3 is on, the signal charge is not completely transferred from the storage region 1 to the vertical CCD register 2, and a portion of the signal charge is transferred to the storage region 1.
This leftover signal charge is then transferred from the storage area 1 to the vertical CCD register 2 when the transfer gate 3 turns on, resulting in the disadvantage that it appears as an afterimage on the playback screen. It was hot.

An object of the present invention is to provide a solid-state imaging device that eliminates the above-mentioned afterimage and a method for driving the same.

According to the present invention, a semiconductor substrate of a first conductivity type, an accumulation region of a second conductivity type formed on the main surface of the substrate and having a conductivity opposite to that of the first conductivity type and accumulating signal charges caused by incident light; a signal charge transfer means provided corresponding to the accumulation region; and a transfer means provided between the accumulation region and the signal charge transfer means for controlling the transfer of signal charges from the accumulation region to the signal charge transfer means. In a unit cell of a solid-state imaging device having an agate, the surface layer of the first conductivity type is provided on the entire surface of the storage region, and the substrate and the Reverse bias voltage between storage region is 30
There is obtained a solid-state imaging device characterized in that it is configured to satisfy the requirement of less than volts.
Furthermore, in the solid-state imaging device of the present invention, when the difference between the Fermi potential when the channel portion of the transfer gate is electrically neutral and the intrinsic Fermi potential is V _F , the inside of the substrate is not depleted. The absolute value V _ch of the channel potential of the transfer gate with reference to the Fermi potential of the part is
A method for driving a solid-state imaging device is obtained, characterized in that charges are transferred from the accumulation region to the signal charge transfer means by setting V _DEP +2V _F or more.

FIG. 5 is a diagram showing the cross section and potential distribution of a single cell according to an embodiment of the present invention, and corresponds to FIG. 4 of the conventional example. The same areas as in the conventional example are indicated by the same symbols.

The present invention will be explained below based on embodiments.

In the solid-state imaging device that eliminates afterimages according to the present invention, the donor concentration in the storage region 1 is lower than that of the conventional device, and a p-type surface layer 7 is provided on the entire surface of the storage region 1. . Therefore, the reverse bias voltage V _DEP required to completely deplete the storage region 1 is small, and V _DEP +2V _F is smaller than the maximum voltage of 30 V of a normal MOS type integrated circuit. V _DEP +2V _F
<30 volts, so V _ch can be greater than V _DEP + 2V _F. In the driving method where V _ch >V _DEP +2V _F , when the transfer gate 3 is turned on and the channel potential reaches V _ch , signal charges begin to transfer from the storage region 1 to the vertical CCD register 2 .
The transfer gate 3 is considered to be a MOSFET, the storage region 1 is considered to be the source, and the vertical CCD register 2 is considered to be the drain. Then, the final potential of V _A
Since V _A <V _ch −2V _F also at V _DEP , this
The MOSFET always operates in a strongly inverted state, charge transfer is performed quickly, storage region 1 is completely depleted, and V _A becomes the final potential V _DEP . For example n
Donor density in type region 1 is 10 ¹⁶ /cm ³ , n-type region 1
Assuming that the junction depth of is 1 μm, and the acceptor density and junction depth of the p-type surface layer are 10 ¹⁸ pieces/cm ³ and 0.5 μm, respectively, V _DEP is as small as about 2.5V. With such an impurity concentration, for example, when the channel length of transfer gate 3 is 5 μm, the channel width is 5 μm, and the capacitance of storage region 1 is 0.03 pF, V _A will vary from about V _DEP −2V.
The time required to reach V _DEP is about 100n _sec at most, which is the time the transfer gate is in the on state.
It is very fast compared to about 1μsec to about 500μsec. As a result, the signal charge is perpendicular to the accumulation region 1.
Completely transferred to CCD register 2, storage area 1
No signal charge is left behind, and no afterimage phenomenon occurs.

P layer provided on the entire surface of the n-type storage region 1
Explain the effect of the surface layer of the mold. FIGS. 2 and 3 are diagrams showing potential distributions when the storage region 1 is viewed in a direction perpendicular to the surface in different embodiments of the present invention. The left side is the surface, and p from the surface
mold surface layer 7, n-type accumulation region 1, and p-type substrate 6
There is. The solid line 8 is the distribution of potential felt by electrons. The one-dot chain line 9 is the Fermi potential in a non-depleted region inside the p-type substrate 6, and is used as a potential standard. These figures show a case where the n-type storage region 1 is completely depleted. FIG. 2 shows that the acceptor concentration in the surface layer 7 is small;
is completely depleted, and FIG. 3 shows a case where the vicinity of the surface of the surface layer 7 is not depleted. In the latter case, the potential of the non-depleted portion of the surface layer 7 is equal to the potential of the non-depleted portion inside the substrate 6. Now, the first effect of the surface layer 7 is
As mentioned above, the goal is to reduce V _DEP . n
Since the type accumulation region 1 not only makes a p-n junction with the p-type substrate 6 but also makes a p-n junction with the p-type surface layer 7, the depletion layer spreads from both p-n junction surfaces. V _DEP becomes smaller. The second effect is that since the maximum potential point is not located at the interface between silicon and the oxide film provided on the silicon surface, signal charges do not come into contact with the interface. As a result, the signal charge is not trapped in the traps distributed near the interface, so that no afterimage occurs due to the traps. Furthermore, in the case of the embodiment shown in FIG.
However, it has the effect of reducing variations in characteristics between lots and devices. Also, since there is no depletion near the interface between silicon and oxide film,
Another effect is that the dark current is small.

This invention uses a signal line as a vertical signal charge transfer means, and this signal line is connected to a horizontal CCD register or horizontal bucket triade ( BBD) connected to the register,
So-called MOS + CCD type two-dimensional solid-state imaging device
It can also be applied to MOS+BBD type two-dimensional solid-state imaging devices. Moreover, it is applicable not only to two-dimensional solid-state imaging devices but also to one-dimensional solid-state imaging devices.

The embodiment of the n-channel type has been described above. In the case of a p-channel type, p and n in the case of an n-channel type may be exchanged, and the absolute value may be used for the signed potential. For example, since the reverse bias voltage V _A between the storage region 1 and the substrate and the difference V F between the Fermi potential of the channel portion of the transfer gate and the intrinsic Fermi potential V _F are usually absolute values, absolute values are also used for the p channel. The channel potential of the transfer gate based on the Fermi potential of the non-depleted portion inside the substrate is positive in the case of an n-channel type and negative in the case of a p-channel type, so the absolute value is used.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a solid-state imaging device, FIG. 4 is a diagram showing a cross section and potential distribution along a unit cell along the - line in FIG. 1, and FIG. 5 is a diagram showing a cross section and potential distribution of a unit cell in the present invention. The figures shown in FIGS. 2 and 3 are diagrams showing potential distributions when the storage region is viewed in a direction perpendicular to the surface in different embodiments of the present invention. 1...Storage region, 2...Signal charge transfer means (vertical CCD register), 3...Transfer gate,
6...Substrate, 7...Surface layer, 9...Felmi potential of the non-depleted portion inside the substrate, V _DEP ...
Reverse bias voltage between the substrate and the storage region required to fully deplete the storage region.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, and an accumulation region of a second conductivity type formed on the main surface of this substrate and having a conductivity type opposite to the first conductivity and accumulating signal charges caused by incident light. ,
a signal charge transfer means provided corresponding to the accumulation region; and a transfer means provided between the accumulation region and the signal charge transfer means for controlling the transfer of signal charges from the accumulation region to the signal charge transfer means. In the unit cell of a solid-state imaging device having agate, the surface layer of the first conductivity type is provided on the entire surface of the storage region, and when the signal charge is transferred from the storage region to the signal charge transfer means, the A solid-state imaging device characterized in that the storage region is completely depleted, and the reverse bias voltage between the substrate and the storage region required for depletion is 30 volts or less. Device. 2. A semiconductor substrate of a first conductivity type, an accumulation region of a second conductivity type formed on a main surface of the substrate and having a conductivity opposite to that of the first conductivity type and accumulating signal charges caused by incident light; A signal charge transfer means provided correspondingly, and a transfer gate provided between the accumulation region and the signal charge transfer means to control transfer of signal charges from the accumulation region to the signal charge transfer means. The surface layer of the first conductivity type is provided on the entire surface of the storage region of the unit cell of the solid-state imaging device, and the amount of contact between the substrate and the storage region is necessary for the storage region to be completely depleted. In a solid-state imaging device configured to satisfy the requirement that the reverse bias voltage V _DEP between When V _F is _the absolute _value of the channel potential of the transfer gate with reference to the Fermi potential of the non- _depleted portion inside the substrate, the accumulation region is A method for driving a solid-state imaging device, characterized in that the storage region is completely depleted by transferring charges from the signal charge transfer means to the signal charge transfer means.