KR20020027021A - CMOS Imae sensor - Google Patents

Abstract

PURPOSE: A complementary-metal-oxide-semiconductor(CMOS) image sensor is provided to minimize the area necessary for an isolation region by forming an isolation layer while using a channel ion implantation process, and to improve a characteristic of the image sensor by exhausting excess charges while using a lateral over flow drain(LOFD) structure. CONSTITUTION: A photodiode(36) converts an image signal regarding light into an electrical image signal. An LOFD transistor(38) laterally exhausts the excess charges generated from the photodiode, wherein one electrode of the LOFD transistor is connected to the photodiode. A transfer signal(TX) is applied to the gate of a transfer transistor(35), wherein one electrode of the transfer transistor is connected to the photodiode and the other electrode of the transfer transistor is connected to a floating node(32). A reset signal(RX) is applied to the gate of a reset transistor(31), wherein one electrode is connected to the floating node and the other electrode of the reset transistor is connected to a reset drain region, so that the charges of the floating node are reset after signal charges are read.

Description

CMOS image sensor {CMOS Imae sensor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor, and more particularly, to a CMOS image sensor capable of efficiently discharging excess charge generated in a photodiode region in a horizontal direction to improve device characteristics.

Most Charge Coupled Devices (CCDs) developed and used for image pickup devices are driven using high voltages (+ 15V, -9V) compared to Complementary Metal Oxide Semiconductor (CMOS) circuits. As it is similar to the process of implementing a bipolar transistor, there is a problem that the process cost is higher than that of a CMOS process.

In order to solve such a problem, research and production of a CMOS image sensor have been made for the purpose of realizing an imaging device in a CMOS process capable of low voltage operation, low power consumption, and low process cost.

Current CMOS image sensors require more research and development due to problems in image quality, although they can be applied to most of the manufacturing processes of CMOS transistors that can be processed very finely.

Hereinafter, a CMOS image sensor and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a pixel circuit of a general CMOS image sensor.

The circuit configuration of the unit cell of the CMOS image sensor includes a reset transistor 11 having a reset signal RX applied to a gate, one electrode connected to a floating node 12, and the other electrode connected to a VDD terminal. A select transistor 13 connected to the floating node 12 and one electrode connected to the VDD terminal, and a column select signal CS are input to the gate and connected in series to the select transistor 13 so that one electrode is connected to an output terminal ( An access transistor 14 connected to Vout), and a transfer transistor 15 having one electrode connected to the floating node 12 and a transfer signal TX input to a gate to transfer charges when the accumulated charges are read. It includes and comprises a photodiode 16 is configured between the transfer transistor 15 and the ground terminal.

In the output terminal Vout, a bias is applied to a gate, and a bias transistor 17 is configured in which the other electrode is connected to the ground terminal.

The charge sensing operation of the CMOS image sensor will be described as follows.

First, charges are accumulated by light incident from the outside to the photodiode 16.

The accumulated signal charge is transmitted to the floating node 12 when the transfer signal is input to the gate of the transfer transistor 15 and turned on.

In this state, the reset transistor 11 remains off and changes the potential of the floating node 12, which is the source terminal of the reset transistor 11, by the signal charge accumulated in the floating node 12, which is a select transistor. The gate potential of (13) is changed.

The change in the gate potential of the select transistor 13 changes the bias of the source terminal of the select transistor 13 or the drain node of the drive transistor 14.

At this time, when the column selection signal is input to the gate of the drive transistor 14, the potential difference due to the signal charge generated by the photodiode 16 is output to the output terminal.

After detecting the signal level by the charge generation of the photodiode 16 in this manner, the reset transistor 11 is turned ON by the reset signal, and the signal charges are all reset.

This process is repeated to read each signal level and to read out the reference potential after reset.

The cross-sectional structure of the unit cell of the CMOS image sensor of the prior art is as follows.

2 is a cross-sectional view of a pixel of a conventional CMOS image sensor.

First, the device isolation layer 22 is formed in the device isolation region of the p-type semiconductor substrate 21 to define an active region.

The photodiode n region 23 and the photodiode p region 24 are formed in the surface of the p-type semiconductor substrate 21.

In this case, the photodiode p region 24 serves as a potential barrier for the electrons to prevent electrons generated from the silicon surface from moving to the lower photodiode n region 23.

An n + region 27 is formed in the p-type semiconductor substrate 21 to be spaced apart from the photodiode regions 23 and 24 and used as a floating diffusion region for sensing image charges.

The transfer gate 25 is formed on the upper side of the p-type semiconductor substrate 21 between the photodiode regions 23 and 24 and the n + region 27.

The reset gate 26 is formed on the other side of the n + region 27.

In the conventional CMOS image sensor configured as described above, a potential barrier is formed on the photodiode p region 24 formed on the upper surface of the photodiode n region 23 so that electrons do not move to the photodiode n region 23. It is configured to prevent but does not completely block the movement of electrons.

In addition, a noise removing circuit may be separately configured to remove electrons on the silicon surface.

The conventional CMOS image sensor has the following problems.

First, a device isolation layer for separating each unit-recovery region is formed by a LOCOS (LOCal Oxidation of Silicon) process to affect the characteristics of the device as the pixel size becomes smaller.

That is, the active region used as the actual device is reduced by the characteristics of the LOCOS process, so it is difficult to secure process margins and secure stable operation characteristics of the device.

Second, in the device isolation structure, when an instantaneous strong light is incident on the photodiode region, the charge is excessively generated, and such an excess charge is transferred to the floating diffusion region.

This is a great cause of lowering the characteristics of the device.

The present invention is to solve the problem of the CMOS image sensor of the prior art, the CMOS to improve the characteristics of the device by efficiently discharging the excess charge generated in the photodiode region in the horizontal direction The purpose is to provide an image sensor.

1 is a pixel circuit diagram of a general CMOS image sensor

2 is a cross-sectional view of a pixel of a conventional CMOS image sensor

3 is a pixel circuit diagram of a CMOS image sensor according to the present invention;

4 is a cross-sectional configuration diagram of a CMOS image sensor according to a first embodiment of the present invention;

5 is a cross-sectional configuration diagram of a CMOS image sensor according to a second embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

31. Reset Transistor 32. Floating Node

33. Select transistor 34. Access transistor

35. Transistor Transistor 36. Photodiode

37.Bias Transistor 38.LOFD Transistor

CMOS image sensor according to the present invention for achieving the above object is a photodiode for converting a video signal for light into an electrical video signal; one electrode is connected to the photodiode to the excess charge generated in the photodiode A horizontal overflow drain (LOFD) transistor configured to discharge in a horizontal direction; a transfer transistor having one electrode connected to the photodiode and the other electrode connected to a floating node, and having a transfer signal TX applied to a gate; (RX) is applied and one electrode is connected to the floating node and the other electrode is connected to the reset drain region so that the unit pixel is configured including a reset transistor for resetting the charge of the floating node after the readout of the signal charge. It is done.

Hereinafter, the CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a pixel circuit diagram of a CMOS image sensor according to the present invention.

The circuit of a CMOS image sensor having a LOFD (LOFD) transistor according to the present invention firstly forms a photodiode 36 which is formed between a VDD terminal and a ground terminal to convert an image signal of incident light into an electrical image signal. ), A horizontal overflow drain (LOFD) transistor 38 connected to one electrode of one side of the photodiode 36 to discharge the excess charge generated in the photodiode 36 in a horizontal direction, and a photodiode 36 Transfers the signal charge of the photodiode 36 to the floating node 32 by a transfer signal TX applied to one of the electrodes on the other side and the other electrode to the floating node 32. The reset transistor RX is applied to the transfer transistor 35 and the gate, one electrode is connected to the floating node 32, and the other electrode is connected to the VDD terminal to read the signal charge. A reset transistor 31 for resetting the charge of the floating node 32, a select transistor 33 whose gate is connected to the floating node 32, and one electrode thereof is connected to the VDD terminal, and a gate select signal ( CS is input and is connected to the select transistor 33 and comprises an access transistor 34, one electrode is connected to the output terminal (Vout).

In the output terminal Vout, a bias is applied to a gate and a bias transistor 37 is connected to the other electrode to a ground terminal.

Here, the gate of the horizontal overflow drain (LOFD) transistor 38 is connected to the VDD terminal to always form a constant channel.

Of course, the channel may be maintained by applying an external DC bias or clock voltage without connecting the gate of the horizontal overflow drain (LOFD) transistor 38 to the VDD terminal.

A cross-sectional structure of a CMOS image sensor having a horizontal overflow drain (LOFD) transistor according to the present invention having such a circuit configuration is as follows.

4 is a cross-sectional configuration diagram of a CMOS image sensor according to a first embodiment of the present invention, and FIG. 5 is a cross-sectional configuration diagram of a CMOS image sensor according to a second embodiment of the present invention.

The first embodiment of the present invention is a device isolation layer formed by an ion implantation process, and the second embodiment of the present invention is a device isolation layer formed by a LOCOS process.

First, in the CMOS image sensor according to the first embodiment of the present invention, as shown in FIG. 4, an isolation layer for device isolation in a predetermined region of a p-type semiconductor substrate (or an n-type semiconductor substrate having p wells) 41 is formed. A 42 is formed by a channel stop ion implantation process, and a photodiode n region 43 and a photodiode p region 44 are formed inside the surface of the p-type semiconductor substrate 41.

In this case, the photodiode p region 44 serves as a potential barrier to prevent electrons generated in the silicon surface region from moving to the photodiode n region 43.

In addition, a floating region 47 is formed on one side of the photodiode including the photodiode n region 43 and the photodiode p region 44 by a distance from the photodiode, and the photodiode and the floating region 47 are formed. The transfer gate 45 is formed on the substrate in between.

The reset drain region 48 is formed to be spaced apart from the floating region 47 on the opposite side of the portion where the transfer gate 45 is formed.

A reset gate 46 is formed on the substrate between the floating region 47 and the reset drain region 48.

As described above, the gate 49 of the horizontal overflow transistor is formed on the device isolation layer 42 formed by the channel stop ion implantation in order to form the unit cell and configure the device in the LOFD structure.

The LOFD gate 49 is connected to an adjacent reset drain region 48 to which VDD is applied.

Here, although the reset drain region 48 to which the LOFD gate 49 is connected is illustrated as the reset drain region 48 of the neighboring pixel in FIG. 4, the reset drain region 48 may be connected to the reset drain region in the pixel.

It is also possible to connect the LOFD gate 49 to a plurality of reset drain regions instead of one in order to increase the reset drain effect of excess charge.

The ion implantation for forming the device isolation layer 42 is formed by implanting impurity ions of the same conductivity type as the substrate or the well, and the ion implantation depth is determined by adjusting the energy and dose during ion implantation.

Of course, it is also possible to use an ion implantation impurity as an impurity opposite to the substrate.

In addition, the ion implantation region for forming the device isolation layer 42 may be formed so as to surround the entire pixel region and may be formed so as to surround only a part of the pixel region.

The ion implantation process for forming the device isolation layer 42 is optionally selected by implanting the photodiode n region 43 and the photodiode p region 44 before or after the formation process or before or after the formation of the gate electrodes. The ion implantation process can be performed after photomasking.

The LOFD gate 49 is formed using a conductive material such as polysilicon or metal.

In Fig. 4 showing the structure of such a unit cell, ① is a region where the device isolation layer 42 having the LOFD gate 49 is formed on the upper side, and ② is a region where the unit pixel is actually formed.

In the CMOS image sensor according to the second embodiment of the present invention, a device isolation layer having a LOCOS structure is formed under the LOFD gate as shown in FIG. 5.

As shown in FIG. 5, a device isolation layer 52 for device isolation is formed in a predetermined region of a p-type semiconductor substrate (or an n-type semiconductor substrate having p wells) 51 by a LOCOS process. The photodiode n region 53 and the photodiode p region 54 are formed inside the surface of 51.

In this case, the photodiode p region 54 serves as a potential barrier to prevent electrons generated in the silicon surface region from moving to the photodiode n region 53.

The photodiode n region 53 and the photodiode p region 54 are formed on one side of the photodiode and are separated from the photodiode by a predetermined distance to form a floating region 57 and the photodiode and the floating region 57. The transfer gate 55 is formed on the substrate in between.

The reset drain region 58 is formed to be spaced apart from the floating region 57 on the opposite side of the portion where the transfer gate 55 is formed.

In addition, a reset gate 56 is formed on the substrate between the floating region 57 and the reset drain region 58.

As described above, the gate 59 of the horizontal overflow transistor is formed on the device isolation layer 52 formed by the LOCOS process in order to form the unit cell and configure the device in the LOFD structure.

The LOFD gate 59 is connected to an adjacent reset drain region 58 to which VDD is applied.

Here, although the reset drain region 58 to which the LOFD gate 59 is connected is illustrated as a reset drain region 58 of neighboring pixels in FIG. 5, the reset drain region 58 may be connected to the reset drain region in the pixel.

It is also possible to connect the LOFD gate 59 to a plurality of reset drain regions instead of one in order to increase the reset drain effect of excess charge.

The impurity ions are implanted into the LOCOS region to adjust the threshold voltage of the horizontal overflow transistor before the LOCOS process is performed.

Impurity ions may be used in the same conductivity type as the substrate or in the opposite conductivity type.

It is also possible to form the gate 59 of the horizontal overflow transistor on the active region instead of the device isolation region, and the width and width of the LOFD gate can be varied without limitation in consideration of process margin and device characteristics. .

In addition, the LOFD gate 49 is formed using a conductive material such as polysilicon or metal.

In Fig. 5 showing the structure of such a unit cell, ① is an area where the device isolation layer 52 in which the LOFD gate 59 is formed is formed, and ② is an area in which the unit pixel is actually formed.

The CMOS image sensor of the present invention allows the photodiode to act as a source of a MOSFET, and the photodiode is discharged to an adjacent reset drain region through a channel region formed by a VDD power source in which excess charge is applied to the LOFD gate. It was made possible.

The CMOS image sensor according to the first and second embodiments of the present invention can be applied differently according to the integration and miniaturization of the device. In the case of the highly integrated and micronized devices, the device isolation region is formed by a channel stop ion implantation process. Otherwise, it is preferable to use the LOCOS process as it is.

This is because efficient discharge of excess charge by the LOFD gate is ensured in both devices with device isolation layers by channel stop ion implantation or LOCOS processes.

Such CMOS image sensor of the present invention has the following effects.

First, since the device isolation layer is formed by channel ion implantation, an area required for the device isolation region can be minimized.

This decreases the specific gravity relative to the total area of the ion implantation area as the size of the pixel decreases, thereby improving the aperture ratio of the device and increasing the pixel integration.

Second, since the device isolation method by ion implantation is used, there is an effect of sufficiently securing the design margin and ease of device.

Third, the discharge of excess charge is discharged using a horizontal overflow drain structure, thereby improving the characteristics of the device.

Fourth, since the voltage applied to the LOFD gate uses VDD, an additional power supply is prevented.

Fifth, the channel potential can be easily adjusted using the concentration of the channel formed in the LOFD region and the gate oxide thickness.

Claims (9)

A photodiode for converting a video signal relating to light into an electrical video signal; A horizontal overflow drain (LOFD) transistor having one electrode connected to the photodiode and discharging excess charge generated in the photodiode in a horizontal direction; A transfer transistor in which one electrode is connected to the photodiode and the other electrode is connected to the floating node so that a transfer signal TX is applied to the gate; A reset pixel RX is applied to the gate, one electrode is connected to the floating node, and the other electrode is connected to the reset drain region. CMOS image sensor, characterized in that configured. The CMOS image sensor of claim 1, wherein a gate of the horizontal overflow drain (LOFD) transistor is connected to the reset drain region and VDD is applied to the reset drain region. The CMOS image sensor of claim 1, wherein VDD is applied to the gate of the horizontal overflow drain (LOFD) transistor or an external DC bias or clock voltage is applied to maintain the channel. 2. The CMOS image sensor of claim 1, wherein the gate of the horizontal overflow drain (LOFD) transistor is formed on an active region or device isolation layer. 5. The CMOS image sensor according to claim 4, wherein the device isolation layer on which the gate of the horizontal overflow drain (LOFD) transistor is formed is a channel stop ion implantation layer or a LOCOS layer. 5. The CMOS image sensor as claimed in claim 1 or 4, wherein the gate of the horizontal overflow drain (LOFD) transistor is connected to a reset drain region of an adjacent pixel or to a reset drain region of the pixel. The method of claim 5, wherein the channel stop ion implantation layer is formed to surround the entire pixel region or to surround only a portion of the pixel region by using impurity ions of the same conductivity type or opposite conductivity type as the substrate or the well. CMOS image sensor. 6. The CMOS image sensor as claimed in claim 5, wherein the same conductivity type or opposite conductivity type impurity ions as the substrate are implanted into the region before the LOCOS layer is formed to adjust the threshold voltage of the horizontal overflow transistor. 2. The CMOS image sensor of claim 1, wherein the gate of the horizontal overflow transistor is formed of a conductive material comprising polysilicon or metal.