JPH0436582B2 - - Google Patents
Info
- Publication number
- JPH0436582B2 JPH0436582B2 JP60196167A JP19616785A JPH0436582B2 JP H0436582 B2 JPH0436582 B2 JP H0436582B2 JP 60196167 A JP60196167 A JP 60196167A JP 19616785 A JP19616785 A JP 19616785A JP H0436582 B2 JPH0436582 B2 JP H0436582B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity layer
- type impurity
- control electrode
- potential
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 11
- 238000003384 imaging method Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 description 44
- 238000009792 diffusion process Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 206010047571 Visual impairment Diseases 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は固体撮像装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a solid-state imaging device.
固体撮像装置は入力された光信号を電気信号に
変換する光電変換素子（例えばフオトダイオー
ド）と、信号電荷を転送する電荷転送部とを有し
ている。
A solid-state imaging device includes a photoelectric conversion element (for example, a photodiode) that converts an input optical signal into an electrical signal, and a charge transfer section that transfers signal charges.
第７図は従来装置の一例の要部の断面図であ
る。ｐ型基板１の光電変換領域にはｎ型不純物層
２が形成され、その位置にp+型不純物層３がよ
り浅く形成されている。このようにして、光信号
を光電変換するためのp+npフオトダイオードが
構成される。また、半導体基板１上には制御電極
４が絶縁層５を介して設けられ、その下には押込
チヤネルをなすｎ型不純物層６が形成されてい
る。そしてp+npフオトダイオード以外の部分は
光遮へい膜７によつて覆われている。 FIG. 7 is a sectional view of a main part of an example of a conventional device. An n-type impurity layer 2 is formed in the photoelectric conversion region of the p-type substrate 1, and a p + -type impurity layer 3 is formed more shallowly at that position. In this way, a p + np photodiode for photoelectrically converting an optical signal is constructed. Further, a control electrode 4 is provided on the semiconductor substrate 1 via an insulating layer 5, and an n-type impurity layer 6 forming a forced channel is formed below the control electrode 4. The portion other than the p + np photodiode is covered with a light shielding film 7.
第８図は第７図に示す従来例のポテンシヤル図
で、第８図中のV2，V6，V8，V9はそれぞれ第７
図中に符号２，６，８，９で示す位置のポテンシ
ヤルに対応している。また、第８図ａは制御電極
４にゼロ電圧を加えた状態を示し、第８図ｂは制
御電極４に高電圧を印加した状態を示す。第８図
ａに示すように、まず信号電荷Q1＋Q2はフオト
ダイオードのｎ型不純物層２に蓄積される。この
状態で制御電極４に高電圧が印加されると、第８
図ｂの如く電荷Q1が埋込チヤネル層（ｎ型不純
物層６）に流れこみ、フオトダイオードのｎ型不
純物層２の端部には電荷Q2が残留する。 FIG. 8 is a potential diagram of the conventional example shown in FIG. 7, and V 2 , V 6 , V 8 , and V 9 in FIG.
This corresponds to the potentials at positions 2, 6, 8, and 9 in the figure. Further, FIG. 8a shows a state in which zero voltage is applied to the control electrode 4, and FIG. 8b shows a state in which a high voltage is applied to the control electrode 4. As shown in FIG. 8a, signal charges Q 1 +Q 2 are first accumulated in the n-type impurity layer 2 of the photodiode. When a high voltage is applied to the control electrode 4 in this state, the eighth
As shown in FIG. b, charge Q 1 flows into the buried channel layer (n-type impurity layer 6), and charge Q 2 remains at the end of the n-type impurity layer 2 of the photodiode.
この残留電荷Q2は第９図に示すように周知の
熱エネルギー分布（ボルツマン分布）をなし、そ
の中で電位V8を越えるのに充分なエネルギーを
有するキヤリアは、拡散過程を経て埋込チヤネル
層６へ長い時間をかけて移動する。この現象は、
埋込チヤネル層６に電荷が存在しないときに顕在
化して偽信号となる。このため、例えば暗い背景
で移動する明るい像を撮像すると、これが残像と
なつて現れる。
This residual charge Q 2 forms a well-known thermal energy distribution (Boltzmann distribution) as shown in Figure 9, in which carriers with sufficient energy to exceed the potential V 8 are channeled through the buried channel through a diffusion process. It takes a long time to move to layer 6. This phenomenon is
This becomes apparent when there is no charge in the buried channel layer 6, resulting in a false signal. For this reason, for example, if a moving bright image is captured against a dark background, this will appear as an afterimage.
このように従来の低残像固体撮像装置では、フ
オトダイオードにp+np構造を採用することでｎ
型不純物層２の電荷を全て読み出すようにしてい
るが、前述の通り残像現象をなくすことはできな
い。これは、制御電極４の下までフオトダイオー
ドのｎ型不純物層が伸びていることに起因するも
のであるが、従来技術ではこれを避けることがで
きない。なぜなら、ｎ型不純物層２を厚く形成す
るためには、熱拡散工程等の製造工程上の制約か
ら制御電極４をｎ型不純物層２形成のマスクとし
て使用することができず、従つて制御電極４とｎ
型不純物層２のある程度のオーバーラツプが不可
避的に生じてしまうからである。 In this way, in conventional solid-state imaging devices with low image retention, by adopting a p + np structure for the photodiode, n
Although all charges in the type impurity layer 2 are read out, as described above, the afterimage phenomenon cannot be eliminated. This is due to the fact that the n-type impurity layer of the photodiode extends below the control electrode 4, but this cannot be avoided with conventional techniques. This is because, in order to form the n-type impurity layer 2 thickly, the control electrode 4 cannot be used as a mask for forming the n-type impurity layer 2 due to constraints in the manufacturing process such as the thermal diffusion process. 4 and n
This is because the type impurity layer 2 inevitably overlaps to some extent.
本発明は上記の従来技術の欠点を克服するため
になされたもので、残留電荷による残像が現れな
いようにした固体撮像装置を提供することを目的
とする。
The present invention was made in order to overcome the above-mentioned drawbacks of the prior art, and it is an object of the present invention to provide a solid-state imaging device that does not cause afterimages due to residual charges.
上記の目的を達成するため本発明は、半導体基
板表面の光電変換領域に形成された第１導電型の
高濃度不純物層と、これと同じ位置により深く形
成された第２導電型の不純物層と、キヤリアを読
出すために絶縁層を介して形成された制御電極
と、高濃度不純物層の端部と制御電極下の基板領
域の端部との間に形成された第２導電型の低濃度
不純物層とを備える固体撮像装置を提供するもの
である。
In order to achieve the above object, the present invention includes a highly concentrated impurity layer of a first conductivity type formed in a photoelectric conversion region on the surface of a semiconductor substrate, and an impurity layer of a second conductivity type formed deeper at the same position. , a control electrode formed via an insulating layer for reading carriers, and a second conductivity type low concentration impurity layer formed between an end of the high concentration impurity layer and an end of the substrate region under the control electrode. An object of the present invention is to provide a solid-state imaging device including an impurity layer.
以下、添附図面の第１図乃至第６図を参照して
本発明のいくつかの実施例を説明する。
Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 1 to 6 of the accompanying drawings.
第１図は一実施例の要部の断面図である。そし
てこれが第７図の従来例と異なる点は、p+型不
純物層１１の下側に広がるｎ型不純物層１２の横
方向の形成範囲がそれぞれ同一であることと、
p+型不純物層１１の端部と制御電極４下の基板
領域の端部との間に低濃度のｎ型不純物層１３が
形成されていることである。このように第１図の
ものでは、制御電極４とｎ型不純物層１３は全く
オーバーラツプしていない。 FIG. 1 is a sectional view of essential parts of one embodiment. This is different from the conventional example shown in FIG. 7 in that the lateral formation range of the n-type impurity layer 12 extending below the p + type impurity layer 11 is the same.
A low concentration n-type impurity layer 13 is formed between the end of the p + -type impurity layer 11 and the end of the substrate region under the control electrode 4 . In this manner, in the structure shown in FIG. 1, the control electrode 4 and the n-type impurity layer 13 do not overlap at all.
次に、第２図により製造工程の一例を説明す
る。まず、第２図ａのように第１のマスク２０を
介してｎ型不純物（例えばリン）をイオン注入
し、熱拡散によつてｎ型不純物１２を形成する。
次いで、第２図ｂのように第２のマスク２１およ
び制御電極４を半導体基板１上に絶縁層を介して
形成し、これらをマスクにしてｎ型不純物を低濃
度でイオン注入する。次いで、制御電極４を残し
たままで熱拡散工程を経ないで第３のマスク２２
を形成し、これをマスクにしてｐ型不純物（例え
ばボロン）を高濃度でイオン注入する。このよう
にすれば、制御電極４とｎ型不純物層１３がオー
バーラツプすることはない。 Next, an example of the manufacturing process will be explained with reference to FIG. First, as shown in FIG. 2a, an n-type impurity (for example, phosphorus) is ion-implanted through a first mask 20, and an n-type impurity 12 is formed by thermal diffusion.
Next, as shown in FIG. 2B, a second mask 21 and a control electrode 4 are formed on the semiconductor substrate 1 via an insulating layer, and using these as masks, n-type impurity ions are implanted at a low concentration. Next, a third mask 22 is applied without going through a thermal diffusion process while leaving the control electrode 4 intact.
is formed, and using this as a mask, a p-type impurity (for example, boron) is ion-implanted at a high concentration. In this way, the control electrode 4 and the n-type impurity layer 13 will not overlap.
次に第３図により作用を説明する。第３図の通
り、ｎ型不純物層１３の空乏化電位V13はｎ型不
純物層１２のキヤリア空乏電位V12より高い。従
つて、制御電極４がゼロ電位のときに発生した信
号電荷Q3が蓄積され（第３図ａ図示）、制御電極
４が高電位のときに信号電荷Q3は全て埋込チヤ
ネルに読み出される（第３図ｂ図示）。すなわち、
光電変換部に電荷が残留することはない。 Next, the operation will be explained with reference to FIG. As shown in FIG. 3, the depletion potential V 13 of the n-type impurity layer 13 is higher than the carrier depletion potential V 12 of the n-type impurity layer 12. Therefore, the signal charge Q3 generated when the control electrode 4 is at zero potential is accumulated (as shown in FIG. 3a), and all of the signal charge Q3 is read out to the buried channel when the control electrode 4 is at a high potential. (Illustrated in Figure 3b). That is,
No charge remains in the photoelectric conversion section.
第４図は本発明の第２の実施例を示している。
そしてこれが第１図のものと異なる点は、p+np
フオトダイオードがｎ型基板３０のｐウエル３１
中に設けられていることと、ｎ型不純物層３２′
がp+型不純物層１１の一部にのみ重複して形成
されていることである。第４図の制御電極４に高
電圧を印加すると、電位分布は第５図のようにな
つて信号電荷は全て読み出される。すなわち、光
電変換部に電荷が残留することはない。 FIG. 4 shows a second embodiment of the invention.
The difference between this and the one in Figure 1 is that p + np
The photodiode is located in the p-well 31 of the n-type substrate 30.
and the n-type impurity layer 32'
is formed overlapping only a part of the p + type impurity layer 11. When a high voltage is applied to the control electrode 4 shown in FIG. 4, the potential distribution becomes as shown in FIG. 5, and all signal charges are read out. That is, no charge remains in the photoelectric conversion section.
このように第２の実施例では、ｎ型不純物層３
２′がp+型不純物層１１の中に延在しているた
め、延在部分のｐ型不純物層の一部が相殺されて
不純物濃度が実効的に減少する。従つて、p+ｎ
接合における接合容量が相殺された分だけわずか
に小さくなり、この部分の空乏化電位がやや高く
なる。そのため、電位分布が第５図のように段階
状になり、電荷転送時間を短くできるという特徴
がある。 In this way, in the second embodiment, the n-type impurity layer 3
2' extends into the p + type impurity layer 11, a portion of the p type impurity layer in the extended portion is canceled out, and the impurity concentration is effectively reduced. Therefore, p + n
The junction capacitance at the junction is canceled out, making it slightly smaller, and the depletion potential at this portion becomes slightly higher. Therefore, the potential distribution becomes stepwise as shown in FIG. 5, and the charge transfer time can be shortened.
第６図は本発明の第３の実施例を示している。
そしてこれが第１図のものと異なる点は、低濃度
のｎ型不純物層４１が埋込チヤネルのｎ型不純物
層６のところまで延びていることである。但し、
ｎ型不純物層６の不純物濃度はｎ型不純物層４１
のそれより高くなければならない。このようにし
た場合には、埋込チヤネルの電荷容量は減少する
が、残留電荷を存在させることはない。 FIG. 6 shows a third embodiment of the invention.
This differs from the one shown in FIG. 1 in that the low concentration n-type impurity layer 41 extends to the n-type impurity layer 6 of the buried channel. however,
The impurity concentration of the n-type impurity layer 6 is the same as that of the n-type impurity layer 41.
must be higher than that of In this case, the charge capacity of the buried channel is reduced, but no residual charge is present.
本発明は上記の実施例に限定されるものではな
く、種々の変形が可能である。例えば半導体基
板、不純物層の導電型は実施例に限定されない。 The present invention is not limited to the above embodiments, and various modifications are possible. For example, the conductivity types of the semiconductor substrate and the impurity layer are not limited to the embodiments.
〔発明の効果〕
上記の通り本発明では、制御電極と光電変換部
の不純物層がオーバーラツプしないようにし、あ
るいは光電変換部の不純物層が埋込チヤネルにま
で達するようにし、光電変換部と電荷転送部の間
にポテンシヤルの井戸が現れないようにしたの
で、残留電荷による残像が現れることのない固体
撮像装置を得ることができる。[Effects of the Invention] As described above, in the present invention, the control electrode and the impurity layer of the photoelectric conversion section are prevented from overlapping, or the impurity layer of the photoelectric conversion section is made to reach the buried channel, and charge transfer between the photoelectric conversion section and the impurity layer is prevented. Since no potential well appears between the parts, it is possible to obtain a solid-state imaging device in which no afterimage due to residual charge appears.
第１図は本発明の第１の実施例の要部断面図、
第２図はその製造工程別断面図、第３図は第１の
実施例のポテンシヤル図、第４図は本発明の第２
の実施例の要部断面図、第５図はそのポテンシヤ
ル図、第６図は本発明の第２の実施例の要部断面
図、第７図は従来装置の一例の要部断面図、第８
図はそのポテンシヤル図、第９図は残留電荷のエ
ネルギー分布図である。
１……ｐ型基板、４……制御電極、５……絶縁
層、６……埋込チヤネルの不純物層、７……光遮
へい膜。
FIG. 1 is a sectional view of a main part of a first embodiment of the present invention,
Figure 2 is a sectional view of the manufacturing process, Figure 3 is a potential diagram of the first embodiment, and Figure 4 is a diagram of the second embodiment of the present invention.
5 is a potential diagram thereof, FIG. 6 is a sectional view of essential parts of the second embodiment of the present invention, and FIG. 7 is a sectional view of essential parts of an example of a conventional device. 8
The figure is a potential diagram, and FIG. 9 is an energy distribution diagram of residual charges. DESCRIPTION OF SYMBOLS 1... P-type substrate, 4... Control electrode, 5... Insulating layer, 6... Impurity layer of buried channel, 7... Light shielding film.
１ 表面濃度が低く、縦方向拡散長の深い第１導
電型の第１のウエル領域と、
前記第１のウエル領域の周縁部にその一部が重
畳するように隣接して延在し、表面濃度が前記第
１のウエル領域の横方向拡散領域の表面濃度より
濃く、かつ縦方向拡散長が前記第１のウエル領域
の縦方向拡散長より浅く形成された第１導電型の
第２のウエル領域と、
これら第１および第２のウエル領域の表面にチ
ヤネルストツプ領域により分離形成され、前記第
１および第２のウエルとの間でpn接合フオトダ
イオードを形成する第２導電型拡散領域と、
前記第２のウエルの外側に、画質に悪影響を与
えない距離だけ離隔して形成されたダイシングラ
イン領域とを備え、
前記チヤネルストツプ領域の一部は前記第２の
ウエルの端部上に形成されたことを特徴とするイ
ンライン型マルチチツプリニアイメージセンサ用
チツプ。
1 a first well region of a first conductivity type with a low surface concentration and a deep vertical diffusion length; a second well of a first conductivity type formed to have a concentration higher than a surface concentration of a lateral diffusion region of the first well region and a vertical diffusion length shallower than a vertical diffusion length of the first well region; a second conductivity type diffusion region formed on the surfaces of the first and second well regions separated by a channel stop region and forming a pn junction photodiode between the first and second well regions; a dicing line region formed outside the second well by a distance that does not adversely affect image quality; and a part of the channel stop region is formed on an end of the second well. An in-line multi-chip linear image sensor chip featuring:
Claims (1)
求の範囲第１項もしくは第２項に記載の固体撮像
装置。The solid-state imaging device according to claim 1 or 2, wherein the absolute value of the potential of the body substrate region is smaller than the absolute value of the potential of the body substrate region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60196167A JPS6255960A (en) | 1985-09-05 | 1985-09-05 | Solid state image pick-up device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60196167A JPS6255960A (en) | 1985-09-05 | 1985-09-05 | Solid state image pick-up device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6255960A JPS6255960A (en) | 1987-03-11 |
| JPH0436582B2 true JPH0436582B2 (en) | 1992-06-16 |
Family
ID=16353320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60196167A Granted JPS6255960A (en) | 1985-09-05 | 1985-09-05 | Solid state image pick-up device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6255960A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306661A (en) * | 1989-05-22 | 1990-12-20 | Nec Corp | Solid-state image sensor |
| US5424574A (en) * | 1992-09-23 | 1995-06-13 | Scientific Imaging Technologies, Inc. | Light shield for a back-side thinned CCD |
| US5401153A (en) * | 1993-11-23 | 1995-03-28 | Yoshizuka Seiki Co., Ltd. | Press for powder metallurgy |
| JP3576033B2 (en) | 1999-03-31 | 2004-10-13 | 株式会社東芝 | Solid-state imaging device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257566A (en) * | 1984-06-04 | 1985-12-19 | Matsushita Electronics Corp | Solid-state image pickup device |
-
1985
- 1985-09-05 JP JP60196167A patent/JPS6255960A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257566A (en) * | 1984-06-04 | 1985-12-19 | Matsushita Electronics Corp | Solid-state image pickup device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6255960A (en) | 1987-03-11 |
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