JP3100624B2 - Non-interlaced interline transfer CCD image sensor with simple electrode structure for each pixel - Google Patents

Description

DETAILED DESCRIPTION OF RELATED APPLICATIONS REFERENCE TO RELATED PATENT APPLICATIONS US Patent Application No. 309,646, filed February 10, 1989, and assigned to the assignee of the present application (Title of Invention: " Interline transfer type CC equipped
D image sensor ": inventor; Losee et al.).

TECHNICAL FIELD The present invention relates to an image sensing device, and more particularly to an interline transfer type charge image sensor for performing non-interlaced readout.

2. Description of the Related Art In an interline transfer type image sensor, photo-generated charges are collected for a predetermined time at a photo charge collecting position or a photoreceptor, such as in a pn junction of a photodiode or below a gate of an optical capacitor, and then transferred to a charge coupled register. It is detected by the output circuit. In such an array of photocharge collection locations, the collected photocharges are first transferred to a vertical shift register and secondly to a horizontal shift register, and finally reach a charge detector or amplifier. In the conventional interlacing device schematically shown in FIGS. 1 and 2, alternating rows of photoreceptors are read out sequentially. The odd number sequence relates to a so-called field, and the even number sequence relates to a second field. In particular, a given column of pixels 10 is addressed by applying a voltage to electrodes 20 and 30. Both electrodes 20 and 30 are connected to the same vertical clock φ1. When a voltage is applied, the photocharge is transferred to the buried channel 40 of the vertical CCD shift register. The vertical shift register consists of a buried channel 40, electrodes 20 and 30.
These are connected to a vertical clock φ1 and electrodes 50 and 60, both electrodes being connected to a vertical clock φ2,
It is isolated from the substrate semiconductor 70 by the insulating layer 80. Regions 65 below electrodes 30 and 60 are implanted to create a potential energy difference between regions 25 and 26 controlled by the Φ1 clock and between regions 55 and 56 controlled by the Φ2 clock. ing. To read image information onto odd numbered light locations, Φ1 is pulsed to transfer charge from the photodiode to the buried channel region below electrode 20. This photo charge is then transferred to the charge detection amplifier via vertical and horizontal CCD shift registers. Then, the position on the even-numbered column is similarly transferred from the even-numbered column of the photodiodes to the buried channel region below the electrode 50, and is read as the second field. However, in such an element configuration, that is, in the non-interlace mode, the vertical shift register cell is provided for each column.
Since only 1/2 is provided, it is not possible to sequentially read from each column of photodiodes. Such non-interlaced readout is preferred if the element is used in an electronic shutter mode for still photography. To achieve non-interlaced readout, a full vertical CCD shift register cell is required for each column of photodiodes. This is because the photocharges from all photodiodes are transferred simultaneously to the vertical shift register and must be held as separate charge packets during the transfer to the output amplifier. To perform such a non-interlaced readout sequence, each pixel must contain at least four individual CCD electrodes if similar manufacturing steps are used and the same number of clock voltages is maintained. Alternatively, Tsaur et a
l in IEEE Electron Device Letters, 10 , 361-36
If three levels of overlapping electrodes are used in a three-phase clock sequence, as disclosed in US Pat. No. 3,1989, non-interlaced readout is possible, but the number of steps increases and the system becomes more complex, further increasing the effective photosensitive area. You have to sacrifice. US Patent No. 4,330,796 (inventor:
Anognostopoulos et al) describe a non-interlaced interline transfer CCD image sensor using three electrodes per pixel, and a "curved channel" CC occupying most of the pixel element or the pixel area.
D is disclosed. However, Losee et al, U.S. Pat.
Curved channel CCD as mentioned in 4,613,402
If the barrier region implants within are not accurately aligned, parasitic potential wells or barriers will be created in the CCD, which will degrade the transfer efficiency and degrade device performance.

DISCLOSURE OF THE INVENTION The present invention has been made in view of the above conventional problems,
An object of the present invention is to provide an image sensor having a simple pixel structure that can operate in a non-interlace mode. It is another object of the present invention to provide an image sensor having a small pixel size. Still another object of the present invention is to provide a non-interlaced image sensor that can use a pixel area more effectively.

The above objects are accomplished in an interline transfer image sensor having a column and row array of individual pixels. In this image sensor, the charge collected in the pixels of each column is transferred into a vertical two-phase CCD. This CCD shift register includes a series of overlapping electrodes. Each electrode is composed of a single level of electrical conductor. Individual voltage clocks are connected to the AC electrodes. Each pair of the electrodes adjacent to each other forms one complete stage of the CCD shift register. Each column pixel corresponds to one pair of electrodes of a vertical CCD. An ion implantation barrier region is formed below the edge of each electrode, and means are provided for transferring charge from each pixel to a region below one of the corresponding electrodes.

The present invention uses a two-phase CCD shift register. C
The CD shift register uses only one electrode for each clock phase. As a result, the ratio of the entire pixel area to the photosensitive area is improved, and a non-interlaced readout element having a simple structure can be realized. This is achieved by providing a vertical CCD shift register with an implanted transfer barrier region, wherein only one layer of the gate electrode is configured as required by each phase of the vertical shift register. In this configuration, only two electrodes need to be provided for each row of the imaging position. According to such a structure,
It does not suffer from limitations due to internal level shorts, such as those caused by photomask failure. Self-alignment of the transfer barrier region implant ensures excellent transfer efficiency in the CCD shift register.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a typical conventional interlaced readout imaging device according to the prior art; FIG. 2 is a cross-sectional view taken along the line AA of FIG. FIGS. 3a-3c are partial plan views showing various stages in the manufacturing process of the interline transfer type surface image sensor according to the present invention; FIGS. 4a, 4b and 4c are A'-A ', B of FIG. 3c. -B and C
FIG. 5 is a partial schematic cross-sectional view according to another embodiment of the present invention.

Modes of the Invention In FIGS. 3 a-c and 4 a-c, the interline transfer type surface image sensor has a semiconductor substrate 100. This board 1
In FIG. 00, a channel stop region 110 and a buried channel region 120 are formed as is clear from FIG. Substrate 100 can be configured as a p-well diffused into an n-type silicon wafer. An insulating oxide film has been grown on the semiconductor surface, and a single level layer of polysilicon conductor 130 has been deposited. U.S. Patent No.
No. 4,631,402 (inventor: Losee et al.) And a barrier region is formed in the region 140 by a method as described in FIG. 3b. 3c and 4b, an insulating layer of oxide 135 has been grown on the polysilicon conductor 130, and the second barrier region has been implanted by appropriate implantation of doped atoms.
160 are formed. A second single level layer of polysilicon conductor is deposited and patterned to form the CCD electrode 170 (see FIG. 4b). The regions 180 not covered by the polysilicon conductor are then implanted with appropriate impurities. This forms the rows and columns of the charge collection location photoreceptor for collecting photogenerated charge.

FIG. 4a discloses a row cross section of an interline surface image sensor having pixels 180. FIG. FIG. 4c shows a cross section of a column of an interline surface image sensor having pixels 180. In this position, layer 170
Is disposed directly above the layer 130. Figure 4b shows two-phase vertical C
3 shows one cross section of a CD shift register. Then, the individual voltage clocks Φ1 and Φ2 are
And 170. As shown, electrode 170 overlaps electrode 130. To operate the device, a positive voltage pulse is applied to the electrode 130, which causes the photogenerated charge from the pixel 180 to pass through the surface channel gap 191 to the buried channel below the electrode 130.
120 (see FIGS. 3a and 3b). Charge is vertical CCD
After being transferred to the shift register, clock voltages Φ1 and Φ2 are applied, and the photocharge is transferred to an appropriate charge detection circuit by a known method. In this way, non-interlaced readout of the photo-generated charges is achieved, and each row of the pixel 180 corresponds to the pair of electrodes 170, 130.

When such an element is used in the electronic shutter mode, a voltage pulse is applied to simultaneously deplete all light receiving positions of arbitrary stored signal charges. For example, if the substrate 10
If 0 is a p-well diffused into an n-type wafer, p
A voltage pulse applied between the well and the n-type wafer can be used to void the light receiving location. After the application of such a dead pulse, a photocharge is generated by absorption of the incident light. Thereafter, when the above-mentioned exposure is performed for an appropriate time, all the accumulated photoreceptive photocharges are simultaneously transferred to the vertical CCD shift register and read out as described above.

FIG. 5 shows another embodiment of the present invention. In this alternative embodiment, the charge collection region 180 of the device is connected via conductive pillars 210 to the capacitor plate. Such conductive pillars are described in J. Electrochemical Soc. 135, 2640 (198
8) It can be produced by the method described in (Raley et al.). The capacitor plate is covered by a photoconductive layer 220 and a top electrode layer 230. The photogenerated charge is transferred across the photoconductive layer and forms a charge collection region 180
Transferred to This photocharge is further transferred from region 180 to a vertical shift register and read out as described in the previous section.

In a third embodiment of the present invention, electrodes 130 and 170 in the figure are made of polysilicon and WSix, MoSix, Tasix, TiSix, W, Mo, or Ta.
And one or more substances selected from the group consisting of:

Example: An example of a device configured according to the present invention will be described below. A p-type region is formed by implanting boron atoms in an amount of 1.0E + 12 cm **-2 into an n-type semiconductor doped to a resistivity of about 30 ohm-cm and diffusing to a depth of about 3.5 μm. Is formed. 1.0E + 13cm **-2
Of boron is formed to form a channel stop barrier region, and then an oxide film having a thickness of about 4000 成長 is grown. By further oxidizing and then etching back, the thickness of this oxide film is reduced to about 2500 °. The buried channel region is formed by implanting arsenic atoms in a total amount of 6.0E + 12 cm **-2, and a transfer gate oxide film having a thickness of about 500 DEG is grown on the photodiode in the charge transfer region. And, the polysilicon electrode and edge aligned boron implanted barrier region are disclosed in U.S. Pat. No. 4,613,402.
(Inventor: Losee et al.)
4.0E + 12 cm **-2 amount of sulfur is injected into the photodiode region. In a high humidity environment, a thin oxide layer is grown at a temperature of 950 ° C. for about 8 minutes. An insulating layer is deposited by chemical vapor deposition. The chemical vapor deposition process was performed on about 10 wt.% Of a silicon oxide layer coated with about 4 wt.% Boron and 4 wt.
It consists of a non-doped oxide film of 00 °. Next, the device is 900 ℃
At 30 ° C. for 30 minutes in an inert atmosphere, the contact openings are etched, and an aluminum interconnect pattern is formed. The pixel size of this element is 9.0 μm in the vertical direction and 9.0 μm in the horizontal direction.

Industrial Applicability When applied to electrophotographic technology, an interline transfer type image sensor using a non-interlaced read sequence is required. In an interline transfer image sensing device, photo-generated charges are transferred from a pixel to a vertical CCD shift register. In a so-called interlaced read sequence, alternating columns of each pixel, including one field, are read one column at a time. The second field consisting of the remaining alternating columns of pixels is then read. The vertical shift CCD register structure in such a device consists of an overlapping level of two or more polysilicon electrodes corresponding to one column of each pixel. However, in electrophotographic technology, this interlaced readout is often unsuitable, and non-interlaced readout, in which photogenerated charges from each column are transferred in a sequence, may be more appropriate. In this disclosure, a non-interlaced interline transfer image sensor having a simple structure and thus improved manufacturability has been described. This device uses a two-phase vertical CCD shift register having an ion-implanted barrier region. Each register is self-alignable, as described in U.S. Pat. No. 4,613,402 (Losee), which allows the manufacture of devices with a minimum of two polysilicon electrodes for each pixel. In addition to structural simplicity, this device provides improved topography for applying integrated color filter arrays and maximizes the light sensitive area.

The preferred embodiment of the present invention has been described above, but it is understood that various changes and improvements can be made within the spirit and scope of the present invention.

──────────────────────────────────────────────────続 き Continuing the front page (72) Inventor Nelson Edward Tea USA New York 14534 Pittsford Brook Road 59 (72) Inventor Treadwell Timothy John USA New York 14450 Fairport County Clare Crescent 79 (56) Reference Document JP-A-58-200574 (JP, A) JP-A-63-23360 (JP, A) JP-A-63-105578 (JP, A) JP-A-63-105579 (JP, A) JP-A 63-105579 285969 (JP, A) JP-A-63-120463 (JP, A) JP-A-58-106966 (JP, A) JP-A-63-81952 (JP, A) JP-A-61-117980 (JP, A) JP-A-59-16472 (JP, A) JP-A-62-9671 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01 L 27/14-27/148 H01L 29/762-29/768

Claims (7)

(57) [Claims] An interline transfer image sensor having an array of columns and rows of individual pixels, comprising: a photoreceptor assigned to each pixel; and a column-side end connected to a respective voltage clock. A series of pairs of electrodes consisting of a single level conductor overlapping each other, a buried channel region formed below the electrodes, and a barrier formed beneath one columnwise edge of each of the paired electrodes. And a pair of electrodes, and the two electrodes forming a pair of electrodes are adjacent to and correspond to each pixel to form one complete stage, and a voltage is applied to one electrode of the pair of electrodes corresponding to each pixel. A vertical two-phase CCD shift register that transfers the charge collected in each pixel to the buried channel region below this electrode by applying A notch is provided at the edge of the lower electrode of the overlap on the pixel outer edge side and the column direction side to expose a region horizontally adjacent to the region between the photoreceptors adjacent in the column direction. An image sensor wherein the barrier region formed below the edge of the upper electrode of the wrap is formed by self-alignment with the edge of the notch. 2. The image sensor according to claim 1, wherein said photoreceptor is formed by injecting an impurity into a region which is not covered by an electrode after said electrode is formed. The generated charge is almost simultaneously CC
An image sensor which is transferred to a D shift register and read out in a non-interlaced format. 3. An image sensor according to claim 1, wherein a voltage is applied to the sensor to deplete the charge collected in all photoreceptors, each photoreceptor having a charge as a function of incident light. An image sensor, wherein the charge from each photoreceptor is collected and simultaneously transferred to a buried channel region below one of the electrodes of the electrode pair corresponding to each pixel. 4. The image sensor according to claim 1, wherein each of said electrodes is made of doped polysilicon. 5. The image sensor according to claim 1, wherein one or both of the pair of electrodes are a composite layer of polysilicon and WSix, MoSix, TaSix, TiSix, W, Mo.
Or an image sensor comprising one or more substances selected from the group consisting of Ta. 6. The image sensor according to claim 1, wherein each photoreceptor includes a photodiode. 7. The image sensor according to claim 1, wherein each photoreceptor includes a light transmitting layer, a capacitor plate connected to the light transmitting layer, a charge collecting region, and a light transmitting layer. Conductive pillars connecting a capacitor to the charge collection region such that the photo-generated charges generated in the charge collection region are transferred to the charge collection region, wherein the charge is then transferred to a vertical CCD shift register. Image sensor.